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PDF V6123 Data sheet ( Hoja de datos )

Número de pieza V6123
Descripción Mux LCD Driver
Fabricantes EM Microelectronic 
Logotipo EM Microelectronic Logotipo



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No Preview Available ! V6123 Hoja de datos, Descripción, Manual

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R EM MICROELECTRONIC - MARIN SA
V6123
Digitally Programmable 2,4 and 8 multiplex LCD Driver
Description
The V6123 is low multiplex LCD driver. The 2, 4 and 8
way multiplex is digitally programmable by the command
byte. The display refresh is handled on chip by an internal
RC oscillator via 1 selectable 8 x 60 RAM which holds the
LCD content driven by the driver. LCD pixels (or
segments) are addressed on a one to one basis with the 8
x 60 bit RAM (a set bit corresponds to an activated LCD
pixel).
The V6123 has very low dynamic current consumption,
typically 175 µA at VDD = 5V, VLCD = 7V making it
particularly attractive for portable and battery powered
products. The wide operating range on supply voltages
and temperature offers much application flexibility. The
LCD bias generation and frame frequency are generated
on chip. The clock signal can be used to shift and to latch
the datas into the RAM.
Applications
Automotive displays
Telephones
Pagers
Portable, battery operated products
Large displays (public information panels etc.)
Balances and scales
Utility meters
Typical Operating Conditions
Features
Very simple 1-bit interface (see Fig.1)
V6123 mux mode 2 with 2 rows and 58 columns
V6123 mux mode 4 with 4 rows and 56 columns
V6123 mux mode 8 with 8 rows and 52 columns
Very simple1-bit interface, reduced to its simplest form
Frame frequency on chip by internal RC oscillator
Voltage bias and mux signal generation on chip
1 display RAM addressable as 8 X 60 bit words
Column driver only mode to have 60 column outputs
No busy states
No external components needed
Blank function for LCD blanking
Bit mapped
Wide VDD voltage supply range, 2 to 6V
Wide VLCD voltage supply range, 2 to 8.5V
-40°C to +85°C temperature range
Pad Assignment
Fig. 1
Copyright © 2004, EM Microelectronic-Marin SA
1
Fig. 2
www.emmicroelectronic.com

1 page




V6123 pdf
R
Block Diagram
Int. Oscillator
FR External Frame
Gating
Bit Sequencer1)
10000000
DO 60 Bit Shift Register
8 Read
Enable Lines
8 x 60 Bit
Display RAM
V6123
Mux Decoder + COL
3
Gating
8 Bit Shift Reg.
DI 8 Write
Enable Lines
CLK
DI
Add. Decoder
Command Bits
FR
VLCD
V1
V2
V3
STR
VSS
LCD
Wafeform
Generator
60 Bit Display Latch
Gating
COL
SET
Blank
60 Display Driver Outputs
S1 … S60
2
Mux Decoder
Fig. 6
Copyright © 2004, EM Microelectronic-Marin SA
5
www.emmicroelectronic.com

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V6123 arduino
R
Applications
Two V6123 8 Mux Programmed Cascaded
V6123
By connecting the V1, V2 and V3 bias inputs as shown, the pixel load is averaged across all the drivers.
The effective bias level source impedance is the parallel combination of the total number of drivers.
For example, if two V6123 are cascaded as above, then the maximum bias level impedance becomes 15 k.
V6123 8 Mux Programmed with External Resistor Divider Bias Generation
Fig. 10
Example set values:
R = 3.3 – 10 k
C = 2.2 – 47 nF
Rx is given by the formula:
Rx = 4R ((VDISP/VLCD)-1) = 10 – 30 k
Copyright © 2004, EM Microelectronic-Marin SA
11
Fig. 11
www.emmicroelectronic.com

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