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PDF OX12PCI840 Data sheet ( Hoja de datos )
| Número de pieza | OX12PCI840 | |
| Descripción | Integrated Parallel Port and PCI interface | |
| Fabricantes | Oxford Semiconductor | |
| Logotipo |  |
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FEATURE
• IEEE1284 SPP/EPP/ECP parallel port
• Single function target PCI controller, fully PCI 2.2 and
PCI Power Management 1.0 compliant
• 2 multi-purpose IO pins which can be configured as
interrupt input pins
DESCRIPTION
The OX12PCI840 is a single chip solution for PCI-based
parallel expansion add-in cards. It is a single function PCI
device.
For legacy applications the PCI resources are arranged so
that the parallel port can be located at standard I/O
addresses.
The efficient 32-bit, 33MHz target-only PCI interface is
compliant with version 2.2 of the PCI Bus Specification and
OX12PCI840
Integrated Parallel Port
and PCI interface
• Can be reconfigured using optional non-volatile
configuration memory (EEPROM)
• 5.0V operation
• 100 pin PQFP package
version 1.0 of PCI Power Management Specification. For
full flexibility, all the default register values can be
overwritten using an optional MicrowireTM serial EEPROM.
The OX12PCI840 provides an IEEE1284 EPP/ECP parallel
port which fully supports the existing Centronics interface.
Oxford Semiconductor Ltd.
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK
Tel: +44 (0)1235 824900 Fax: +44(0)1235 821141
© Oxford Semiconductor 1999
OX12PCI840 1.2 – Dec 2001
Part No. OX12PCI840-PQC-A
1 page  
OXFORD SEMICONDUCTOR LTD.
OX12PCI840
2 PIN DESCRIPTIONS
Pin Numbers
Dir1 Name
PCI interface
89,90,91,93,94,95,98,99,2,4,5,6,9,
10,11,12,26,27,28,31,32,33,34,36,
38,39,42,43,46,47,49,50
100,13,25,37
86
14
19
17
18
21
24
23
22
1
84
83
88
P_I/O
P_I
P_I
P_I
P_O
P_I
P_O
P_O
P_I/O
P_O
P_I/O
P_I
P_I
P_OD
P_OD
AD[31:0]
C/BE[3:0]#
CLK
FRAME#
DEVSEL#
IRDY#
TRDY#
STOP#
PAR
SERR#
PERR#
IDSEL
RST#
INTA#
PME#
Description
Multiplexed PCI Address/Data bus
PCI Command/Byte enable
PCI system clock
Cycle Frame
Device Select
Initiator ready
Target ready
Target Stop request
Parity
System error
Parity error
Initialisation device select
PCI system reset
PCI interrupt
Power management event
Data Sheet Revision 1.2
Page 5
5 Page 
OXFORD SEMICONDUCTOR LTD.
OX12PCI840
4.3 Accessing logical functions
Access to the parallel port is achieved via standard I/O and memory mapping, at addresses defined by the Base Address
Registers (BARs) in configuration space. The BARs are configured by the system to allocate blocks of I/O and memory space to
the logical function, according to the size required by the function. The addresses allocated can then be used to access the
function. The mapping of these BARs is shown in Table 4.
BAR Mapping
0 Parallel port base registers (I/O mapped)
1 Parallel port extended registers (I/O mapped)
2 Local configuration registers (I/O mapped
3 Local configuration registers (memory mapped)
4 Unused
5 Unused
Table 4: Base Address Register definition
4.3.1 PCI access to parallel port
Access to the port works with two I/O BARs corresponding
to the two sets of registers defined to operate an IEEE1284
ECP/EPP and bi-directional Parallel Port.
The user can change the I/O space block size of BAR0 or
BAR by over-writing the default values using the serial
EEPROM (see section 4.4).
Legacy parallel ports expect the upper register set to be
mapped 0x400 above the base block, therefore if the BARs
are fixed with this relationship, generic parallel port drivers
can be used to operate the device in all modes.
Example: BAR0 = 0x00000379 (8 bytes at address 0x378)
BAR1 = 0x00000779 (8 bytes at address 0x778)
If this relationship is not used, custom drivers will be
needed.
Data Sheet Revision 1.2
Page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet OX12PCI840.PDF ] | |
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