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PDF VRS51L3174 Data sheet ( Hoja de datos )

Número de pieza VRS51L3174
Descripción FRAM-Enhanced High Performance 8051 MCU
Fabricantes Ramtron Corporation 
Logotipo Ramtron Corporation Logotipo



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VRS51L3174www.DataSheet4U.com
Datasheet
Rev 1.0
High-Performance 8051 MCU + 8KB FRAM
Overview
The VRS51L3174 is a high performance, 8051-based microcontroller
coupled with a fully integrated array of peripherals for addressing a
broad range of embedded design applications.
Based on a powerful 40-MIPS, single-cycle, 8051 microprocessor,
the VRS51L3174’s memory sub-system features 64KB of Flash
and 4352 bytes of SRAM and 8192 Bytes of nonvolatile FRAM
(ferroelectric random access memory) memory.
Support peripherals include a hardware based arithmetic unit capable
of performing complex mathematical operations, a JTAG interface for
Flash programming and non-intrusive in-circuit debugging/emulation,
an internal oscillator, and a watchdog timer.
Communication and control of external devices is facilitated via an
assortment of digital peripherals such as an enhanced, fully
configurable SPI bus, an I²C interface, dual UARTs with dedicated
baud rate generators, three 16-bit timers, 8 PWM controllers each
with a 16-bit timer, and 2 pulse width counter modules.
The VRS51L3174 operates from 3.0 to 3.6 volts over the industrial
temperature range and is available in a QFP-44 package. The device
features an active-low reset and is pin-compatible with an industry
standard 8051 microcontroller footprint.
FIGURE 1: VRS51L3174 FUNCTIONAL DIAGRAM
Feature Set
o 8051 High Performance Single Cycle Processor
(Operation up to 40 MIPS)
o 64KB Flash Program Memory
(In-System/ln-Application Programmable)
o 4352 Bytes of SRAM (4KB + 256)
(Ext. 4KB can be used for program or data memory)
o 8192 Bytes of on-chip FRAM memory
o JTAG Interface for Flash Programming and Non-Intrusive
Debugging/In-Circuit Emulation
o MULT/DIV/ACCU Unit including Barrel Shifter
o 40 General Purpose I/Os
o 2 Serial UARTs/2 Baud Rate Generators (20-bit resolution)
o Enhanced SPI Interface (fully configurable word size)
o Fully Configurable I2C Interface (Master/Slave)
o 16 External Interrupt Pins/Interrupt On Port Pin Change
o 16-bit General Purpose Timer/Counters
o 2 Pulse Width Counter Modules
o 8 PWM Controller Outputs with Individual Timers
o PWMs can be used as General Purpose Timers
o Internal Oscillator
o Dynamic System Clock Frequency Adjustment
o Power Saving Features
o Power-On Reset/Brown-Out Detect
o Watchdog Timer
o Operating voltage: 3.0V to 3.6V
o Operating Temperature -40°C to +85°C
FIGURE 2: VRS51L3174 QFP-44
Ramtron International Corporation http://www.ramtron.com
1850 Ramtron Drive Colorado Springs [email protected]
Colorado, USA, 80921 1-800-545-FRAM, 1-719-481-7000
page 1 of 114

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VRS51L3174 pdf
www.VDaRtaSShe5et14UL.c3om174
UART0INT
UART0CFG
UART0BUF
UART0BRL
UART0BRH
UART0EXT
Reserved
INTEN2
PWMCFG
PWMEN
PWMLDPOL
PWMDATA
PWMTMREN
PWMTMRF
PWMCLKCFG
P3
UART1INT
UART1CFG
UART1BUF
UART1BRL
UART1BRH
UART1EXT
Not used
IPINFLAG1
PORTCHG
P4
SPICTRL
SPICONFIG
SPISIZE
SPIRXTX0
SPIRXTX1
SPIRXTX2
SPIRXTX3
Reserved
SPISTATUS
PSW
I2CCONFIG
I2CTIMING
I2CIDCFG
I2CSTATUS
I2CRXTX
IPININV1
A1h
A2h
A3h
A4h
A5h
A6h
A7h
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
D0h
D1h
D2h
D3h
D4h
D5h
D6h
COLEN
BRADJ3
U0TIMERF
PCHGIEN1
-
PWM7EN
PWM7LDPOL
PWM7TMREN
PWM7TMRF
U4PWMCLK3
-
COLEN
BRADJ3
U1TIMERF
P37IF
PMONFLAG1
SPICLK2
SPIMANCS
SPIREVERSE
CY
MASTRARB
I2CID6
I2CERROR
P37IINV
RXOVEN
BRADJ2
U0TIMEREN
AUWDTIEN
PWMWAIT
PWM6EN
PWM6LDPOL
PWM6TMREN
PWM6TMRF
U4PWMCLK2
-
RXOVEN
BRADJ2
U1TIMEREN
P36IF
PCHGMSK1
SPICLK1
SPIUNDERC
-
AC
I2CRXOVEN
I2CID5
I2CNOACK
P36IINV
RXAVAILEN
BRADJ1
TXEMPTYEN
BRADJ0
COLENF
BRCLKSRC
RXOVF
B9RXTX
U0RXSTATE MULTIPROC J1708PRI3
J1708PRI2
PWMT47IEN
PWMCLRALL
PWM5EN
PWM5LDPOL
PWMT03IEN
PWMLSBMSB
PWM4EN
PWM4LDPOL
PWCIEN
PWMMIDEND
PWM3EN
PWM3LDPOL
I2CUARTCI
PWMCH2
PWM2EN
PWM2LDPOL
PWM5TMREN
PWM5TMRF
U4PWMCLK1
-
RXAVAILEN
BRADJ1
PWM4TMREN
PWM4TMRF
U4PWMCLK0
-
TXEMPTYEN
BRADJ0
PWM3TMREN
PWM3TMRF
L4PWMCLK3
-
COLENF
BRCLKSRC
PWM2TMREN
PWM2TMRF
L4PWMDCLK2
-
RXOVF
B9RXTX
U1RXSTATE MULTIPROC J1708PRI3
J1708PRI2
P35IF
PCHGSEL1
P34IF
PCHGSEL0
P31IF
PMONFLAG0
P30IF
PCHGMSK0
SPICLK0
FSONCS3
SPICS1
SPILOADCS3
SPICS0
SPISLOW
SPICLKPH
SPIRXOVEN
SPIUNDERF
F0
I2CRXAVEN
SSPINVAL
RS1
I2CTXEEN
SPINOCS
RS0
I2CMASTART
SPIRXOVF
OV
I2CSCLLOW
I2CID4
I2CSDASYNC
I2CID3
I2CACKPH
I2CID2
I2CIDLEF
I2CID1
I2CRXOVF
P35IINV
P34IINV
P33IINV
P32IINV
RXAVENF
B9EN
J1708PRI1
I2CIEN
PWMCH1
PWM1EN
PWM1LDPOL
PWM1TMREN
PWM1TMRF
L4PWMCLK1
-
RXAVENF
B9EN
J1708PRI1
INT1IF
PCHGSEL1
SPICLKPOL
SPIRXAVEN
SPIRXAVF
F1
I2CRXSTOP
I2CID0
I2CRXAVF
INT1IINV
TXEMPTYF
STOP2EN
J1708PRI0
T2IEN
PWMCH0
PWM0EN
PWM0LDPOL
PWM0TMREN
PWM0TMRF
L4PWMCLK0
-
TXEMPTYF
STOP2EN
J1708PRI0
INT0IF
PCHGSEL0
SPIMASTER
SPITXEEN
SPITXEMPF
P
I2CMODE
I2CADVCFG
I2CTXEMPF
INT0IINV
1111b
0000
0001b
1110
0000b
0000
0000b
0000
0000b
0000
0000b
0010
0000b
0000
0000b
0000
0000b
0000
0000b
0000
0000b
0000
0000b
0000
0000b
0000
0000b
0000
0000b
1111
1011b
0000
0001b
1110
0000b
0000
0000b
0000
0000b
0000
0000b
0010
0000b
0000
0000b
0000
0000b
1111
1111b
0000
0001b
0000
0000b
0000
0111b
0000
0000b
0000
0000b
0000
0000b
0000
0000b
1111
1111b
0011
1001b
0000
0000b
0000 0100b
0000 1100b
0000 0000b
0010 1001b
0000 0000b
0000
0000b
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VRS51L3174 arduino
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1 VRS51L3174 Registers & SFR
1.1 Accumulator, B and User Flags
Register
The VRS51L3174 accumulator is located at address
E0h on SFR pages 0 and 1. The accumulator is the
source and destination for many 8051 instructions.
TABLE 7: THE ACCUMULATOR - ACC OR A SFR E0H
7 6543
2
1
0
R/W, Reset = 0x00
ACC[7:0]
The B register is mainly used for MUL and DIV
instructions, holding the MSB of the MUL instruction
and the remainder of the DIV instruction. It can also
be used as a general purpose register that is bit-
addressable. It is accessible on both SFR pages 0 and
1 at address F0h.
TABLE 8: B REGISTER - SFR F0H
7 6543
2
1
0
R/W, Reset = 0x00
B[7:0]
1.2 PSW Register
The PSW register is a bit-addressable register that
contains the status flags (CY, AC, OV, P), user flag
(F0) and register bank select bits (RS1, RS0) of the
8051 processor.
TABLE 9:THE PSW SFR REGISTER - PSW SFR D0H
7 65 4
3
R/W R/W R/W R/W
R/W
0 00 0
0
2
R/W
0
1
R/W
0
0
R/W
0
Bit Mnemonic Description
7 CY
Carry Bit Flag. Indicates that the last
addition/subtraction resulted in a carry or
borrow. The CY bit is cleared by other arithmetic
instructions, the JBC and CLR C instructions.
6 AC
Auxiliary Carry Bit Flag. Indicates that the last
addition/subtraction resulted in a carry or borrow
from the higher nibble. The AC bit is cleared by
other arithmetic instructions and by the JBC
instruction.
5 F0
User General Purpose Flag
4:3 RS1:RS0
Register Select Address Bank for R0 – R7
00 R0 to R7 From 00h to 07h
01 R0 to R7 From 08h to 0Fh
10 R0 to R7 From 10h to 17h
11 R0 to R7 From 17h to 1Fh
2 OV
Overflow Flag
Indicates that the last addition/subtraction
resulted in a carry/borrow/overflow. The OV bit
is cleared by other arithmetic instructions and
the JBC instruction.
1 F1
User General Purpose Flag
0P
Parity Flag
1.3 Data Pointers
The VRS51L3174 includes two 16-bit data pointers
that are described in the following tables. The active
data pointer is controlled via a DPS register located at
SFR address 86h (see below).
TABLE 10: DATA POINTER 0 HIGH - DPH0 SFR 83H
7 6543
2
R/W, Reset = 0x00
DPTR0[15:8]
TABLE 11: DATA POINTER 0 LOW - DPL0 SFR 82H
7 6543
2
R/W, Reset = 0x00
DPTR0[7:0]
TABLE 12: DATA POINTER 1 HIGH - DPH1 SFR 85H
7 6543
2
R/W, Reset = 0x00
DPTR1[15:8]
TABLE 13: DATA POINTER 1 LOW - DPL1 SFR 84H
7 6543
2
R/W, Reset = 0x00
DPTR1[7:0]
TABLE 14: DATA POINTER SELECT REGISTER - DPS SFR 86H
7 65 4 3 2
R RR R
R
R
0 00 0
0
0
1
1
1
1
1
R
0
0
0
0
0
0
R/W
0
Bit Mnemonic Description
7:1 unused
0 DPSEL
DPS value
0 : Selects DPTR 0
1 : Selects DPTR 1
1.4 Stack Pointer
The stack pointer is a register located at address 81h
of the SFR register area whose value corresponds to
the address of the last item that was put on the
processor stack. Each time new data is put on the
processor stack, the value of the stack pointer is
incremented.
TABLE 15: STACK POINTER - SP SFR 81H
7 6543
2
1
0
R/W, Reset = 0x07
SP[7:0]
By default, the stack pointer value is 07h. The stack
can be set anywhere in the internal SRAM from
address 00h to FFh.
Each time a function call is performed or an interrupt is
serviced, the 16-bit return address (2 bytes) is stored
on the stack. Data can be manually placed on the
stack by using the PUSH and POP functions.
www.ramtron.com
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