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PDF XR16M2752 Data sheet ( Hoja de datos )
| Número de pieza | XR16M2752 | |
| Descripción | HIGH PERFORMANCE DUART | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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XR16M2752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
JUNE 2007
REV. P1.0.0
GENERAL DESCRIPTION
The XR16M27521 (M2752) is a high performance
dual universal asynchronous receiver and transmitter
(UART) with 64 byte TX and RX FIFOs. The device
operates from 1.62 to 3.6 volts and is pin-to-pin
compatible to Exar’s ST16C2552, XR16L2552,
XR16L2752 and XR16V2752. The M2752 register set
is identical to the XR16V2752 and is compatible to
the ST16C2552 and the XR16C2852 enhanced
features. It supports the Exar’s enhanced features of
programmable FIFO trigger level and FIFO level
counters, automatic hardware (RTS/CTS) and
software flow control, automatic RS-485 half duplex
direction control output and a complete modem
interface. Onboard registers provide the user with
operational status and data error flags. An internal
loopback capability allows system diagnostics.
Independent programmable baud rate generators are
provided in each channel to select data rates up to 8
Mbps at 3.3 Volt and 8X sampling clock. The M2752
is available in 44-pin PLCC and 32-pin QFN
packages.
NOTE: 1 Covered by U.S. Patent #5,649,122
APPLICATIONS
• Portable Appliances
• Telecommunication Network Routers
• Ethernet Network Routers
• Cellular Data Devices
• Factory Automation and Process Controls
FEATURES
• 1.62 to 3.6 Volt Operation
• Pin-to-pin compatible to Exar’s XR16L2752
• Two independent UART channels
■ Register set compatible to XR16L2752
■ Data rate of up to 8 Mbps at 3.3 V, 6.25 Mbps
at 2.5 V and 4 Mbps at 1.8 V with 8X sampling
rate
■ Fractional Baud Rate Generator
■ Transmit and Receive FIFOs of 64 bytes
■ Programmable TX and RX FIFO Trigger Levels
■ Transmit and Receive FIFO Level Counters
■ Automatic Hardware (RTS/CTS) Flow Control
■ Selectable Auto RTS Flow Control Hysteresis
■ Automatic Software (Xon/Xoff) Flow Control
■ Automatic RS-485 Half-duplex Direction
Control Output via RTS#
■ Wireless Infrared (IrDA 1.0) Encoder/Decoder
■ Automatic sleep mode
■ Full modem interface
• Alternate Function Register
• Device Identification and Revision
• Crystal oscillator or external clock input
• Crystal oscillator (up to 32MHz) or external clock
(up to 64MHz) input
• 44-PLCC and 32-QFN packages
FIGURE 1. XR16M2752 BLOCK DIAGRAM
A2:A0
D7:D0
IOR#
IOW#
CS#
CHSEL
INTA
INTB
TXRDYA#
TXRDYB#
MFA#
(OP2A#,
BAUDOUTA#, or
RXRDYA#)
MFB#
(OP2B#,
BAUDOUTB#, or
RXRDYB#)
Reset
8-bit Data
Bus
Interface
UART Channel A
UART
Regs
BRG
64 Byte TX FIFO
TX & RX IR
ENDEC
64 Byte RX FIFO
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
Modem Control Logic
1.62 V to 3.6 V VCC
GND
TXA (or TXIRA)
RXA (or RXIRA)
TXB (or TXIRB)
RXB (or RXIRB)
XTAL1
XTAL2
CTS#A/B, RI#A/B,
CD#A/B, DSR#A/B
DTR#A/B, RTS#A/B
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
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REV. P1.0.0
Pin Description
NAME
RTSB#
32-QFN
PIN #
13
CTSB#
17
DTRB#
DSRB#
-
-
CDB#
-
RIB#
-
MFB#
-
44-PLCC
PIN #
23
28
27
29
30
31
19
XR16M2752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
TYPE
DESCRIPTION
O UART channel B Request-to-Send (active low) or general purpose output.
This port must be asserted prior to using auto RTS flow control, see
EFR[6], MCR[1], FCTR[1:0], EMSR[5:4] and IER[6]. For auto RS485 half-
duplex direction control, see FCTR[3] and EMSR[3].
I UART channel B Clear-to-Send (active low) or general purpose input. It
can be used for auto CTS flow control, see EFR[7], and IER[7]. This input
should be connected to VCC when not used.
O UART channel B Data-Terminal-Ready (active low) or general purpose
output. If this pin is not used, leave it unconnected.
I UART channel B Data-Set-Ready (active low) or general purpose input.
This input should be connected to VCC when not used. This input has no
effect on the UART.
I UART channel B Carrier-Detect (active low) or general purpose input. This
input should be connected to VCC when not used. This input has no effect
on the UART.
I UART channel B Ring-Indicator (active low) or general purpose input. This
input should be connected to VCC when not used. This input has no effect
on the UART.
O Multi-Function Output Channel B. This output pin can function as the
OP2B#, BAUDOUTB#, or RXRDYB# pin. One of these output signal func-
tions can be selected by the user programmable bits 1-2 of the Alternate
Function Register (AFR). These signal functions are described as follows:
ANCILLARY SIGNALS
XTAL1
4
XTAL2
5
RESET
12
11
13
21
VCC
GND
GND
26
20
Center Pad
44, 33
22, 12
N/A
NC 18, 19
-
1) OP2B# - When OP2B# (active low) is selected, the MF# pin is LOW
when MCR bit-3 is set HIGH (see MCR bit-3). MCR bit-3 defaults to a logic
0 condition after a reset or power-up.
2) BAUDOUTB# - When BAUDOUTB# function is selected, the 16X Baud
rate clock output is available at this pin.
3) RXRDYB# - RXRDYB# (active low) is intended for monitoring DMA data
transfers. See Table 2 for more details.
I Crystal or external clock input.
O Crystal or buffered clock output.
I Reset (active high) - A longer than 40 ns HIGH pulse on this pin will reset
the internal registers and all outputs. The UART transmitter output will be
held HIGH, the receiver input will be ignored and outputs are reset during
reset period (see Table 16).
Pwr 1.62 to 3.6V power supply.
Pwr Power supply common, ground.
Pwr The center pad on the backside of the 32-QFN package is metallic and
should be connected to GND on the PCB. The thermal pad size on the
PCB should be the approximate size of this center pad and should be sol-
der mask defined. The solder mask opening should be at least 0.0025"
inwards from the edge of the PCB thermal pad.
- No Connect.
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
5
5 Page 
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REV. P1.0.0
XR16M2752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
FIGURE 5. BAUD RATE GENERATOR
To Other
Channel
XTAL1
XTAL2
Crystal
Osc/
Buffer
Prescaler
Divide by 1
Prescaler
Divide by 4
DLL, DLM and DLD
Registers
MCR Bit-7=0
(default)
Fractional Baud
Rate Generator
Logic
16X or 8X
Sampling
Rate Clock
to Transmitter
and Receiver
MCR Bit-7=1
TABLE 5: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING
Required
Output Data
Rate
400
2400
4800
9600
10000
19200
25000
28800
38400
50000
57600
75000
100000
115200
153600
200000
225000
230400
250000
300000
400000
460800
500000
750000
921600
1000000
DIVISOR FOR
16x Clock
(Decimal)
3750
625
312.5
156.25
150
78.125
60
52.0833
39.0625
30
26.0417
20
15
13.0208
9.7656
7.5
6.6667
6.5104
6
5
3.75
3.2552
3
2
1.6276
1.5
DIVISOR
OBTAINABLE IN
M2752
3750
625
312 8/16
156 4/16
150
78 2/16
60
52 1/16
39 1/16
30
26 1/16
20
15
13
9 12/16
7 8/16
6 11/16
6 8/16
6
5
3 12/16
3 4/16
3
2
1 10/16
1 8/16
DLM PROGRAM
VALUE (HEX)
E
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DLL PROGRAM DLD PROGRAM
VALUE (HEX) VALUE (HEX)
A6 0
71 0
38 8
9C 4
96 0
4E 2
3C 0
34 1
27 1
1E 0
1A 1
14 0
F0
D0
9C
78
6B
68
60
50
3C
34
30
20
1A
18
DATA ERROR
RATE (%)
0
0
0
0
0
0
0
0.04
0
0
0.08
0
0
0.16
0.16
0
0.31
0.16
0
0
0
0.16
0
0
0.16
0
11
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| Páginas | Total 52 Páginas | |
| PDF Descargar | [ Datasheet XR16M2752.PDF ] | |
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