|
|
PDF FM22L16 Data sheet ( Hoja de datos )
| Número de pieza | FM22L16 | |
| Descripción | 4Mbit Ferroelectric Nonvolatile RAM | |
| Fabricantes | Ramtron | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de FM22L16 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
Preliminary
FM22L16
4Mbit FRAM Memory
Features
4Mbit Ferroelectric Nonvolatile RAM
• Organized as 256Kx16
• Configurable as 512Kx8 Using /UB, /LB
• 1014 Read/Write Cycles
• NoDelay™ Writes
• Page Mode Operation to 40MHz
• Advanced High-Reliability Ferroelectric Process
SRAM Compatible
• JEDEC 256Kx16 SRAM Pinout
• 55 ns Access Time, 110 ns Cycle Time
Advanced Features
• Low VDD Monitor Protects Memory against
Inadvertent Writes
• Software Programmable Block Write Protect
Description
The FM22L16 is a 256Kx16 nonvolatile memory that
reads and writes like a standard SRAM. A
ferroelectric random access memory or FRAM is
nonvolatile, which means that data is retained after
power is removed. It provides data retention for over
10 years while eliminating the reliability concerns,
functional disadvantages, and system design
complexities of battery-backed SRAM (BBSRAM).
Fast write timing and high write endurance make
FRAM superior to other types of memory.
In-system operation of the FM22L16 is very similar
to other RAM devices and can be used as a drop-in
replacement for standard SRAM. Read and write
cycles may be triggered by /CE or simply by
changing the address. The FRAM memory is
nonvolatile due to its unique ferroelectric memory
process. These features make the FM22L16 ideal for
nonvolatile memory applications requiring frequent
or rapid writes in the form of an SRAM.
The FM22L16 includes a low voltage monitor that
blocks access to the memory array when VDD drops
below a critical threshold. The memory is protected
against an inadvertent access and data corruption
under this condition. The device also features
software-controlled write protection. The memory
Superior to Battery-backed SRAM Modules
• No Battery Concerns
• Monolithic Reliability
• True Surface Mount Solution, No Rework Steps
• Superior for Moisture, Shock, and Vibration
Low Power Operation
• 2.7V – 3.6V Power Supply
• Low Current Mode (5µA) using ZZ pin
• 18 mA Active Current
Industry Standard Configuration
• Industrial Temperature -40° C to +85° C
• 44-pin “Green”/RoHS TSOP-II package
array is divided into 8 uniform blocks, each of which
can be individually write protected.
The device is available in a 400 mil 44-pin TSOP-II
surface mount package. Device specifications are
guaranteed over industrial temperature range –40°C
to +85°C.
Pin Configuration
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VDD
VSS
DQ4
DQ5
DQ6
DQ7
WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 A5
43 A6
42 A7
41 OE
40 UB
39 LB
38 DQ15
37 DQ14
36 DQ13
35 DQ12
34 VSS
33 VDD
32 DQ11
31 DQ10
30 DQ9
29 DQ8
28 /ZZ
27 A8
26 A9
25 A10
24 A11
23 A12
Ordering Information
FM22L16-55-TG 55 ns access, 44-pin
“Green”/RoHS TSOP-II
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Rev. 1.0
March 2007
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Page 1 of 15
1 page  
www.DataSheet4U.com
Precharge Operation
The precharge operation is an internal condition in
which the state of the memory is being prepared for a
new access. Precharge is user-initiated by driving the
/CE signal high. It must remain high for at least the
minimum precharge time tPC.
Software Write Protection
The 256Kx16 address space is divided into 8 sectors
(blocks) of 32Kx16 each. Each sector can be
individually software write-protected and the settings
are nonvolatile. A unique address and command
sequence invokes the write protection mode.
To modify write protection, the system host must
issue six read commands, three write commands, and
a final read command. The specific sequence of read
addresses must be provided in order to access to the
write protect mode. Following the read address
sequence, the host must write a data byte that
specifies the desired protection state of each sector.
For confirmation, the system must then write the
complement of the protection byte immediately
following the protection byte. Any error that occurs
including read addresses in the wrong order, issuing a
seventh read address, or failing to complement the
protection value will leave the write protection
unchanged.
The write protect state machine monitors all
addresses, taking no action until this particular
read/write sequence occurs. During the address
sequence, each read will occur as a valid operation
and data from the corresponding addresses will be
driven onto the data bus. Any address that occurs out
of sequence will cause the software protection state
machine to start over. After the address sequence is
completed, the next operation must be a write cycle.
The data byte contains the write-protect settings. This
value will not be written to the memory array, so the
address is a don’t-care. Rather it will be held pending
the next cycle, which must be a write of the data
complement to the protection settings. If the
complement is correct, the write protect settings will
be adjusted. If not, the process is aborted and the
address sequence starts over. The data value written
FM22L16
after the correct six addresses will not be entered into
memory.
The protection data byte consists of 8-bits, each
associated with the write protect state of a sector. The
data byte must be driven to the lower 8-bits of the
data bus, DQ(7:0). Setting a bit to 1 write protects the
corresponding sector; a 0 enables writes for that
sector. The following table shows the write-protect
sectors with the corresponding bit that controls the
write-protect setting.
Write Protect Sectors – 32K x16 blocks
Sector 7
3FFFFh – 38000h
Sector 6
37FFFh – 30000h
Sector 5
2FFFFh – 28000h
Sector 4
27FFFh – 20000h
Sector 3
1FFFFh – 18000h
Sector 2
17FFFh – 10000h
Sector 1
0FFFFh – 08000h
Sector 0
07FFFh – 00000h
The write-protect read address sequence follows:
1. 24555h *
2. 3AAAAh
3. 02333h
4. 1CCCCh
5. 000FFh
6. 3EF00h
7. 3AAAAh
8. 1CCCCh
9. 0FF00h
10. 00000h
* If /CE is low entering the sequence, then an
address of 00000h must precede 24555h.
The address sequence provides a very secure way of
modifying the protection. The write-protect sequence
has a 1 in 3 x 1032 chance of randomly accessing
exactly the 1st six addresses. The odds are further
reduced by requiring three more write cycles, one that
requires an exact inversion of the data byte. A flow
chart of the entire write protect operation is shown in
Figure 2. The write-protect settings are nonvolatile.
The factory default: all blocks are unprotected.
Rev. 1.0
March 2007
Page 5 of 15
5 Page 
www.DataSheet4U.com
Page Mode Read Cycle Timing
FM22L16
* Although sequential column addressing is shown, it is not required.
Write Cycle Timing 1 (/WE-Controlled, /OE low)
Write Cycle Timing 2 (/CE-Controlled)
Rev. 1.0
March 2007
Page 11 of 15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet FM22L16.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| FM22L16 | 4-Mbit (256K x 16) F-RAM Memory |  Cypress Semiconductor |
| FM22L16 | 4Mbit Ferroelectric Nonvolatile RAM | Ramtron |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |