PDF D16550 Data sheet ( Hoja de datos )

Número de pieza	D16550
Descripción	Configurable UART
Fabricantes	Lattice Semiconductor
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No Preview Available ! www.DataSheet4U.com D16550 Configurable UART with FIFO ver 2.11 OVERVIEW The D16550 is a soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C550A. The D16550 allows serial transmission in two modes: UART mode and FIFO mode. In FIFO mode internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit directions. D16550 performs serial-to- parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt). D16550 includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (216-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions are also included to use this 16 × clock to drive the receiver logic. The D16550 has complete MODEM control capability, and a processor-interrupt system. Interrupts can be programmed to the user's requirements, minimizing the computing required to handle the communications link. The separate BAUD CLK line allow to set an exact transmission speed, while the UART All trademarks mentioned in this document are trademarks of their respective owners. internal logic is clocked with the CPU frequency. Two DMA modes are supported: single transfer and multi-transfer. These modes allow UART to interface to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers. The configuration capability allows user to enable or disable during Synthesis process the Modem Control Logic and FIFO's Control Logic, change the FIFO size. So in applications with area limitation and where the UART works only in 16450 mode, disabling Modem Control and FIFO's allow to save about 50% of logic resources. The D16550 has universal microcontroller interface, allows correct communication with D16550 no matter how D16550 clock is related to microcontroller clock. The core is perfect for applications, where the UART Core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip, as well as for standalone implementation, where several UARTs are required to be implemented inside a single chip, and driven by some off-chip devices. Thanks to universal interface D16550 core implementation and verification are very simply, by eliminating a number of clock trees in complete system. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. 1 page www.DataSheet4U.com DLL or DLM to prevent long counts on initial load. Modem Control Logic controls the interface with the MODEM or data set (or a peripheral device emulating a MODEM). Interrupt Controller - D16550 consists fully prioritized interrupt system controller. It controls interrupt requests to the CPU and interrupt priority. Interrupt controller contains Interrupt Enable (IER) and Interrupt Identification (IIR) registers. Receiver Control - Receiving starts when the falling edge on Serial Input (SI) during IDLE State is detected. After starting the SI input is sampled every 16 internal baud cycles as it is shown in figure below. When the logic 1 state is detected during START bit it means that the False Start bit was detected and receiver back to the IDLE state. Receiver FIFO - The Rx FIFO is 16 levels deep, it receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it holds 16 of them. It will not accept any more data when it is full. Any more data entering the Rx shift register will set the Overrun Error flag. Transmitter Control module controls transmission of written to THR (Transmitter Holding register) character via serial output SO. The new transmission starts on the next overflow signal of internal baud generator, after writing to THR register or Transmitter FIFO. Transmission control contains THR register and transmitter shift register. Transmitter FIFO - the Tx portion of the UART transmits data through SO as soon as the CPU loads a byte into the Tx FIFO. The UART will prevent loads to the Tx FIFO if it currently holds 16 characters. Loading to the Tx FIFO will again be enabled as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx. The UART starts the above operations typically with a Tx interrupt. PERFORMANCE The following table gives a survey about the Core area and performance in the LATTICE® devices after Place & Route (all key features have been included): Device SC1 ECP21 ECP2M1 XP21 XP1 ECP1 EC1 ispXPGA1 ORCA 41 ORCA 31 Speed grade -7 -7 -7 -7 -5 -5 -5 -4 -3 -7 LUTs/PFUs 541 / 232 529 / 232 410 / 228 410 / 227 569 / 239 569 / 239 569 / 239 415 / 144 410 / 92 385 / 78 1- FIFOs implemented in RAM’s – 304 Bits Fmax 253 MHz 177 MHz 177 MHz 130 MHz 130 MHz 143 MHz 166 MHz 78 MHz 72 MHz 47 MHz Core performance in LATTICE® devices All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. 5 Page

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