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PDF NCN6804 Data sheet ( Hoja de datos )

Número de pieza NCN6804
Descripción Dual Smart Card Interface
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NCN6804
Dual Smart Card Interface
IC with SPI Programming
Interface
The NCN6804 is a dual interface IC with serial control. It is
dedicated for Smart Card/Secure Access Module (SAM) reader/writer
applications. It allows the management of two external ISO/EMV
cards (Class A, B or C). An SPI bus is used to control and configure
the dual interface. The cards are controlled in a multiplexed mode.
Two NCN6804 devices (4 smart card interfaces) can share one single
control bus thanks to a dedicated hardware address pin (S1).
An accurate protection system guarantees timely and controlled
shutdown in the case of external error conditions.
This device is an enhanced version of the NCN6004A, more
compact, more flexible and fully compatible with the NCN6001, its
single interface counterpart version. It is fully compatible with ISO
7816-3, EMV and GIE-CB standards.
Features
ăDual Smart Card / SAM Interface with SPI Programming Bus
ăFully Compatible with ISO 7816-3, EMV and GIE-CB Standards
ăOne Protected Bidirectional Buffered I/O Line per Card Port
ăWide Power Supply Voltage Range: 2.7V < VDDPA/B & VDD < 5.5V
ăProgrammable/Independent CRD_VCC Supply for Each Smart Card
ăMultiplexed Mode of Operating
ăHandles 1.8 V, 3.0 V and 5.0 V Smart Cards
ăProgrammable Rise & Fall Card Clock Slopes (Slow & Fast Modes)
ăSupport up to 40 MHz Clock with Internal Programmable Clock
(division ratio 1/1, 1/2, 1/4) Managed Independently for Each Card
ăBuilt-in Programmable CRD_CLK Stop Function handles Low State
ăESD Protection on Card pins (8 kV, Human Body Model)
ăActivation / Deactivation built-in Sequencer
ăInternal I/O Pull-up Resistor with Resistor Disconnection Option
(EN_RPU)
ă4–Wire Series Bus Interface – SPI
ăQFN32 (5x5 mm2) Package
ăThis is a Pb-Free Device
Typical Application
ăPoint Of Sales (POS) and Transaction Terminals
ăATM (Automatic Teller Machine) / Banking Terminal Interfaces
ăSet Top Box Decoder and Pay TV
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1 32
QFN32
CASE 488AM
MARKING
DIAGRAM
1
NCN
6804
ALYWG
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb-Free Package
PIN CONNECTIONS
32 31 30 29 28 27 26 25
S1
CRD_DETA
CRD_C4A
CRD_C8A
CRD_I/OA
CRD_RSTA
CRD_CLKA
CRD_VCCA
1
2
3
4
5
6
7
8
EXPOSED PAD
33
GNDD
24 INT
23 CRD_DETB
22 CRD_C4B
21 CRD_C8B
20 CRD_I/OB
19 CRD_RSTB
18 CRD_CLKB
17 CRD_VCCB
9 10 11 12 13 14 15 16
ORDERING INFORMATION
Device
Package
Shipping
NCN6804MNR2G QFN32
(Pb-Free)
3000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
©Ă Semiconductor Components Industries, LLC, 2007
May, 2007 - Rev. 0
1
Publication Order Number:
NCN6804/D

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NCN6804 pdf
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NCN6804
PIN FUNCTION AND DESCRIPTION
PIN Name Type
Description
25 I/O
I/O This pin is connected to an external micro-controller (mC) interface. A bi-directional level translator
adapts the serial I/O signal between the smart card and the mC. The level translator is enabled when
CS = LOW, the sub address has been selected and the system operates in the Asynchronous mode.
When a Synchronous card is in use this pin is disconnected and the data and transaction take place
through the MOSI and the MISO registers. The internal pull up resistor connected on the mC side is
activated and visible by the selected chip only.
26 CLK_IN
I This pin (high impedance) can be connected to either the mC master clock or to a crystal oscillator
clock to drive the external smart cards. The signal is fed to the internal clock selector circuit and
translated to the CRD_CLKA or CRD_CLKB pins at either the same frequency, or divided by 2, 4 or
8, depending upon the programming mode. Refer to table 2. Synchronous case: clock managed
through the SPI bus – CLK_IN is disconnected. Note: The chip guarantees the EMV 50% Duty Cycle
when the clock divider ratio is 1/2, 1/4, or 1/8, even when the CLK_IN signal is out of the 45% to 55%
range specified by ISO and EMV specifications.
27 CS
I This pin synchronizes and enables the SPI communication. All the NCN6804 functions, both
programming and card transaction, are disabled when CS = HIGH.
28 CLK_SPI
Clock Signal to synchronize the SPI data transfer. This clock is fully independent from the CLK_IN
signal and does not play any role with the data transaction (I/O – CRD_I/O).
29 MISO
O Master In Slave Out: SPI Data Output from the NCN6804. This STATUS byte carries the state of the
interface, the serial transfer being achieved according to the programmed mode (Table 2), using the
same CLK_SPI signal and during the same MOSI time frame. An external 4.7 kW pull down resistor
might be necessary to avoid misunderstanding of the pin 29 voltage during the High Z state.
30 MOSI
I Master Out Slave In: SPI Data Input from the mC. This byte contains the address of the selected chip
among the two possible (bit b6), together with the programming code for a given interface. See Table
2.
31 EN_RPU
I This pin is used to activate the I/O internal pull-up resistor such as:
EN_RPU = Low => I/O Pull-up resistor disconnected
EN_RPU = High => I/O Pull-up resistor connected
When two or more NCN6804 chips share the same I/O bus, one chip only shall have the internal
pull-up resistor enabled to avoid any overload of the I/O line. Moreover, when Asynchronous and
Synchronous cards are handled by the interfaces, the activated I/O pull-up resistor must preferably
be the one associated with the asynchronous circuit. On the other hand, since no internal pull-up
bias resistor is built in the chip, pin 31 must be connected to the right voltage level to make sure the
logic function is satisfied.
32
VDD
Power This pin is connected to the system controller power supply (Cbypass_min = 100 nF). When VDD is
below 2.5 V the CRD_VCCA or B is disabled. The NCN6804 goes into a shutdown mode.
33
GNDD
Power Digital/analog Ground. This pin is the Exposed Pad and is the Ground for the digital/analog circuit
section. It needs to be connected to the PCB Ground.
ATTRIBUTES
Characteristics
ESD protection
Human Body Model, Smart Card Pins (Card Interface Pins (Card A
and B)) (Note 1)
Human Body Model, CRD_DETA/B Pins (2, 23) (Note 1)
Human Body Model, All Other Pins (Note 1)
Moisture sensitivity (Note 2) QFN-32
Flammability Rating Oxygen Index: 28 to 34
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. Human Body Model (HBM), R = 1500 W, C = 100 pF.
2. For additional information, see Application Note AND8003/D.
Values
8 kV
4 kV
2 kV
Level 1
UL 94 V-0 @ 0.125 in
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NCN6804 arduino
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NCN6804
Table 1. WRT_REG BIT DEFINITIONS
b2 If (b7 + b6 + b5 ) = 000 or (b7 + b6 + b5 ) = 010 then
b3 Case 00
CRD_CLKA = Low
Case 01
CRD_CLKA = CLK_IN
Case 10
CRD_CLKA = CLK_IN / 2
Case 11
CRD_CLKA = CLK_IN / 4
Else if (b7 + b6 + b5 ) = 001 or (b7 + b6 + b5 ) = 011 then
Case 00
CRD_CLKB = Low
Case 01
CRD_CLKB = CLK_IN
Case 10
CRD_CLKB = CLK_IN / 2
Case 11
CRD_CLKB = CLK_IN / 4
Else if (b7 + b6 + b5) =110 or (b7 + b6 + b5) = 111 then
b3 drives CRD_CLKA or B (respectively)
b2 drives CRD_IOA or B (respectively)
Else if (b7 + b6 + b5) =101 then
Case 00
CRD_CLKA & B = SLO_SLP
Case 01
CRD_CLKA & B = FST_SLP
Case 10
NA
Case 11
NA
Else if (b7 + b6 + b5) =100 then
NA (Not Applicable)
End if
b4 If (b7 + b6 + b5) <> 101 and (b7 + b6 + b5) <> 100 then b4 Drives CRD_RSTA or B Pin
b5 000 Select NCN6804 device # 1 Asynchronous Card A (Note 8)
b6 001 Select NCN6804 device # 1 Asynchronous Card B (Note 8)
b7 010 Select NCN6804 device # 2 Asynchronous Card A (Note 8)
011 Select NCN6804 device # 2 Asynchronous Card B (Note 8)
100 NA
101 Set Card Detection Switch polarity, Set SPI_MODE normal or special , Set CRD_CLKA & B slopes Fast or Slow
110 Select External Synchronous Card A
111 Select External Synchronous Card B
8. When operating in Asynchronous mode, b6 is compared with the external voltage level present pin S1 (Pin 1).
9. The CRD_RST pin reflects the content of the MOSI WRT_REG [b4] during the chip programming sequence. Since the bit shall be Low
to address the chip's internal register, care must be observed as this signal will be immediately transferred to the CRD_RST pin.
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