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PDF BD3531F Data sheet ( Hoja de datos )
| Número de pieza | BD3531F | |
| Descripción | Termination Regulator | |
| Fabricantes | ROHM Semiconductor | |
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Datasheet
Termination Regulator for DDR-SDRAMs
BD3531F
General Description
BD3531F is a termination regulator that complies with
JEDEC requirements for DDR-SDRAM. This linear
power supply uses a built-in N-channel MOSFET and
high-speed OP-AMPS specially designed to provide
excellent transient response. It has a sink/source
current capability up to 1.5A and has a power supply
bias requirement of 5.0V for driving the N-channel
MOSFET. By employing an independent reference
voltage input (VDDQ) and a feedback pin (VTTS), this
termination regulator provides excellent output voltage
accuracy and load regulation as required by JEDEC
standards. Additionally, BD3531F has a reference
power supply output (VREF) for DDR-SDRAM or for
memory controllers. Unlike the VTT output that goes to
“Hi-Z” state, the VREF output is kept unchanged when
EN input is changed to “Low”, making this IC suitable
for DDR-SDRAM under “Self Refresh” state.
Features
Incorporates a Push-Pull Power Supply for
Termination (VTT)
Incorporates a Reference Voltage Circuit (VREF)
Incorporates an Enabler
Incorporates an Undervoltage Lockout (UVLO)
Incorporates a Thermal Shutdown Protector (TSD)
Compatible with Dual Channel (DDR-II)
Applications
Power supply for DDR I/II - SDRAM
Key Specifications
Termination Input Voltage Range: 1.0V to 5.5V
VCC Input Voltage Range:
4.5V to 5.5V
Output Voltage:
1/2xVVDDQ V(Typ)
Output Current:
1.5A(Max)
High Side FET ON-Resistance:
0.4Ω(Typ)
Low side FET ON-Resistance:
0.4Ω(Typ)
Standby Current:
0.8mA (Typ)
Operating Temperature Range: -10°C to +100°C
Package
W(Typ) x D(Typ) x H(Max)
SOP8
5.00mm x 6.20mm x 1.71mm
Typical Application Circuit, Block Diagram
VCC
VDDQ
VTT_IN
VCC
Reference
Block
VDDQ
VCC
50kΩ
UVLO
VCC
50kΩ
UVLO
Enable
EN
Thermal
Protection
TSD
GND
VCC
VTT_IN
TSD
VCC EN
UVLO
TSD
EN
UVLO
VTT
VTTS
VREF
VTT
½x
VDDQ
○Product structure：Silicon monolithic integrated circuit
www.rohm.com
© 2015 ROHM Co., Ltd. All rights reserved.
TSZ22111・14・001
○This product has no designed protection against radioactive rays
1/15
TSZ02201-0J2J0A900950-1-2
02.Nov.2015 Rev.001
1 page  
BD3531F
Typical Waveforms
VVTT(10mV/Div)
IVTT(1A/Div)
10μsec/Div
Figure 1. DDR I
(-1A → +1A)
VVTT(10mV/Div)
IVTT(1A/Div)
10μsec/Div
Figure 3. DDR II
(-1A → +1A)
VVTT(10mV/Div)
IVTT(1A/Div)
10μsec/Div
Figure 2. DDR I
(+1A → -1A)
VVTT(10mV/Div)
IVTT(1A/Div)
10μsec/Div
Figure 4. DDRII
(+1A → -1A)
www.rohm.com
© 2015 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
5/15
TSZ02201-0J2J0A900950-1-2
02.Nov.2015 Rev.001
5 Page 
BD3531F
Operational Notes – continued
12. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should
be avoided.
Resistor
Transistor (NPN)
Pin A
Pin A
Pin B
C
B
E
Pin B
P+
NN
Parasitic
Elements
P P+
NN
P Substrate
GND
Parasitic
Elements
N P+
N P N P+ N
P Substrate
Parasitic
GND GND
Elements
Figure 13. Example of monolithic IC structure
B
N Region
close-by
C
E
Parasitic
Elements
GND
13. Thermal Shutdown Circuit(TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s power dissipation rating. If however the rating is exceeded for a continued period, the junction
temperature (Tj) will exceed 175°C which will activate the TSD circuit that will turn OFF all output pins. When the Tj
falls below the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.
14. Capacitor Across Output and GND
If a large capacitor is connected between the output pin and ground pin, current from the charged capacitor can flow
into the output pin and may destroy the IC when the VCC or IN pin is shorted to ground or pulled down to 0V. Use a
capacitor smaller than 1000µF between output and ground.
15. Output Capacitor
Do not fail to connect a output capacitor and resister to VREF output terminal for stabilization of output voltage. The
capacitor connected to VREF output terminal works as a loop gain phase compensator. Insufficient capacitance and
resister may cause an oscillation. It is recommended to use a low temperature coefficient 2.2μF ceramic capacitor and
0.5Ω resister though it depends on ambient temperature and load conditions. It is therefore requested to carefully
check under the actual temperature and load conditions to be applied.
16. Output Capacitor
Do not fail to connect a capacitor to VTT output pin for stabilization of output voltage. This output capacitor works as a
loop gain phase compensator and an output voltage variation reducer in the event of sudden change in load.
Insufficient capacitance may cause an oscillation. And if the equivalent series resistance (ESR) of this capacitor is high,
the variation in output voltage increases in the event of sudden change in load. It is recommended to use a 220μF
functional polymer capacitor, though it depends on ambient temperature and load conditions. Using a low ESR ceramic
capacitor may reduce a loop gain phase margin and cause an oscillation, which may be improved by connecting a
resistor in series with the capacitor. It is therefore requested to carefully check under the actual temperature and load
conditions to be applied.
www.rohm.com
© 2015 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
11/15
TSZ02201-0J2J0A900950-1-2
02.Nov.2015 Rev.001
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet BD3531F.PDF ] | |
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