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PDF BD3508EKN Data sheet ( Hoja de datos )
| Número de pieza | BD3508EKN | |
| Descripción | Ultra Low Dropout Linear Regulators | |
| Fabricantes | ROHM Semiconductor | |
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TECHNICAL NOTE
High-performance Regulator IC Series for PCs
Ultra Low Dropout
Linear Regulators for PC Chipsets
BD3508EKN
● Description
The BD3508EKN ultra low-dropout linear chipset regulator operates from a very low input supply, and offers ideal
performance in low input voltage to low output voltage applications. It incorporates a built-in N-MOSFET power transistor to
minimize the input-to-output voltage differential to the ON resistance (RON=65mΩ) level. By lowering the dropout voltage in
this way, the regulator realizes high current output (Iomax=3.0A) with reduced conversion loss, and thereby obviates the
switching regulator and its power transistor, choke coil, and rectifier diode. Thus, the BD3508EKN is designed to enable
significant package profile downsizing and cost reduction. An external resistor allows the entire range of output voltage
configurations between 0.65 and 2.7V, while the NRCS (soft start) function enables a controlled output voltage ramp-up,
which can be programmed to whatever power supply sequence is required.
● Features
1) Internal high-precision reference voltage circuit(0.65V±1%)
2) Built-in VCC under voltage lock out circuit (VCC=3.80V)
3) NRCS (soft start) function reduces the magnitude of in-rush current
4) Internal Nch MOSFET driver offers low ON resistance (65mΩ typ)
5) Built-in current limit circuit(3.0A min)
6) Built-in thermal shutdown (TSD) circuit
7) Variable output (0.65～2.7V)
8) Incorporates high-power HQFN20V package: 4.2×4.2×0.9(mm)
● Applications
Notebook computers, Desktop computers, LCD-TV, DVD, Digital appliances
● Model Lineup
Oct. 2008
1 page  
VCC
Ven
VIN
Vo
VIN→Ven→VCC
Fig.13 Input sequence
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
-10 10 30 50 70 90 100
Ta(℃)
Fig.16 Ta-ICC
30
25
20
15
10
5
0
-60 -30 0
30 60 90 120 150
Ta(℃)
Fig.19 Ta-IINSTB
10
9
8
7
6
5
4
3
2
1
0
-10 10 30 50 70 90 100
Ta(℃)
Fig.22 Ta-Ien
VCC
Ven
VIN
Vo
Ven→VIN→VCC
Fig.14 Input sequence
1.2
1
0.8
0.6
0.4
0.2
0
-60 -30 0 30 60 90 120 150
Ta(℃)
Fig.17 Ta-ISTB
25
24
23
22
21
20
19
18
17
16
15
-10 10 30 50 70 90 100
Ta(℃)
Fig.20 Ta-INRCS
60
50
40
30
20
10
0
-10 10 30 50 70 90 100
Ta(℃)
Fig.23 Ta-RON
(VCC=5V/Vo=1.2V)
1.25
1.23
1.21
1.19
1.17
1.15
-10 10 30 50 70 90 100
Ta(℃)
Fig.15 Ta-Vo (Io=0mA)
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
-10 10 30 50 70 90 100
Ta(℃)
Fig.18 Ta-IIN
20
15
10
5
0
-5
-10
-15
-20
-10 10 30 50 70 90 100
Ta(℃)
Fig.21 Ta-IFB
60
55
50
1.8V
45
2.5V
40
35
30 1.2V
25
24 6
Vcc(V)
8
Fig.24 VCC-RON
5 Page 
● Heat Loss
Thermal design should allow operation within the following conditions. Note that the temperatures listed are the allowed
temperature limits, and thermal design should allow sufficient margin from the limits.
1. Ambient temperature Ta can be no higher than 100 ℃.
2. Chip junction temperature (Tj) can be no higher than 150℃.
Chip junction temperature can be determined as follows:
① Calculation based on ambient temperature (Ta)
Tj=Ta+θj-a×W
＜Reference values＞
θj-a:HQFN20V 250.0℃/W Bare (unmounted) IC
166.7℃/W 1-layer substrate (top layer copper foil less than 3%)
71.4℃/W 1-layer substrate (bottom layer surface copper foil area 60×60mm2)
62.5℃/W 2-layer substrate (top layer copper foil area 60×60mm2)
Substrate size: 70×70×1.6mm3 (substrate with thermal via)
It is recommended to layout the VIA for heat radiation in the GND pattern of reverse (of IC) when there is the GND pattern in
the inner layer (in using multiplayer substrate). This package is so small (size: 4.2mm×4.2mm) that it is not available to
layout the VIA in the bottom of IC. Spreading the pattern and being increased the number of VIA like the figure below).
enable to get the superior heat radiation characteristic. (This figure is the image. It is recommended that the VIA size and
the number is designed suitable for the actual situation.).
Most of the heat loss that occurs in the BD3508EKN is generated from the output Nch FET. Power loss is determined by
the total VIN-Vo voltage and output current. Be sure to confirm the system input and output voltage and the output current
conditions in relation to the heat dissipation characteristics of the VIN and Vo in the design. Bearing in mind that heat
dissipation may vary substantially depending on the substrate employed (due to the power package incorporated in the
BD3508EKN) make certain to factor conditions such as substrate size into the thermal design.
Power consumption (W) = Input voltage (VIN)- output voltage (Vo) ×Io (Ave)
Example) VIN=1.5V, Vo=1.2V, Io(Ave) = 3A
Power consumption (W) = 1.5(V)-1.2(V) ×3.0(A)
= 0.9(W)
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet BD3508EKN.PDF ] | |
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