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PDF V6310 Data sheet ( Hoja de datos )

Número de pieza V6310
Descripción Ultra Low Power 3-Pin Voltage Window Surveillance
Fabricantes EM Microelectronic 
Logotipo EM Microelectronic Logotipo



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No Preview Available ! V6310 Hoja de datos, Descripción, Manual

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R
EM MICROELECTRONIC-MARIN SA
V6310
Ultra Low Power 3-Pin Voltage Window Surveillance
with Time-out
Features
n Voltage Window monitoring
n Clear microprocessor restart after power up
n Processor reset at power down
n Reset output guaranteed down to VDD = 1 V
n Low power consumption: typ. 3 mA at VDD = 5 V
n - 40 to +85 OC temperature range
n On request extended temperature range, -40 to +125 OC
n On-chip oscillator
n No external components required
n Push-pull or Open drain output
n TO-92, SOT-23 5L and SOT-223 1) packages
n Pin compatible with DS 1233 A in TO-92 and SOT-223
1) On request
Description
The V6310 is a CMOS device which monitors the supply voltage
of any electronic system, and generates the appropriate Reset
signal. The g ap between the two thresholds defines the
allowed voltage range. As long as VDD stays inside this voltage
window, the output stays inactive. If VDD drops below VTHlow, or
rises above VTHhigh, the output gets active. When V DD enters into
the allowed range, the output remains active for an additional 50
ms (typ.). This allows the system to stabilize before getting fully
active. The lower thresho ld voltage may be obtained in
different versions:
2.0 V to 6 V
2.4 V to 6 V
2.8 V to 6 V
3.5 V to 6 V
4.0 V to 6 V
4.5 V to 6 V
Applications
All microprocessor applications where an automatic restart is
required:
n Computer electronics
n White / Brown goods
n Automotive electronics
n Industrial electronics
n Telecom systems
n Hand-held systems
Typical Operating Configuration
VDD
VDD
V6310
VSS
RES
or
RES
VDD
RES
or
Micro-
RES processor
VSS
GND
For Open drain version:
Fig. 1
Pin Assignment
TO-92
View
Flat Front
V6310
12 3
VDD
RES
or
VSS
RES
SOT-223 1)
VSS
SOT-23 5L
NC VSS NC
4
V6310
1 23
3 21
V6310
45
RES or
RES
VSS
1) On request
VDD
RES or
RES
VDD
Fig. 2
1

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