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PDF L9A0212 Data sheet ( Hoja de datos )

Número de pieza L9A0212
Descripción Microprocessor
Fabricantes LSI 
Logotipo LSI Logotipo



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TinyRISC® LR4102
Microprocessor
Datasheet
The TinyRISC LR4102 Microprocessor is a compact, high performance
32-bit microprocessor implemented in the LSI Logic G11™ technology.
The LR4102 is a complete microprocessor solution with caches, an
external bus interface with built-in memory controllers, and on-chip
debug. The LR4102 is built using the EZ4102 EasyMACRO subsystem,
available to customers through the LSI Logic CoreWare® program.
The LR4102 provides a 32-bit FBusMACRO to control all off-chip data
transactions (including DRAM or SDRAM) and an EJTAG interface for
on-chip debug with PC trace output. Figure 1 illustrates the LR4102 chip.
Figure 1 LR4102 Block Diagram
LR4102
www.DataSheet4U.com
Clock
Controller
MMU
32-bit TinyRISC
4102 CPU
and FastMDU
BIU and Cache
Controller (BBCC)
Two 32-bit Timers
SerialICE™-1 Port
EJTAG
TLB RAM
Caches
OCM
FBus-
MACRO
FBus
SerialICE-1
Interface
EJTAG
Interface
EJTAG
Extended Debug MACRO
PC Trace
Output
The LR4102 microprocessor is powered by either 2.5 V (for 85 MHz
operation) or 1.8 V (for 50 MHz operation). The chip I/O ring requires
3.3 V. With a system clock of 85 MHz, peak performance is 85 MIPS and
sustained performance is estimated at 68 MIPS. With a 50 MHz clock,
performance is 50 MIPS peak and 40 MIPS sustained.
March 2000
Copyright © 1998–2000 by LSI Logic Corporation. All rights reserved.
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L9A0212 pdf
Instruction Set Summary
Table 1
Table 1 summarizes the 32-bit instruction set for the LR4102, and Table
2 lists the unimplemented MIPS II instructions. Table 3 provides a
summary of the LR4102 MIPS16 instruction set.
LR4102 32-Bit Instruction Set Summary
Load and Store Instructions
LB
LBU
LH
LHU
LW
LWL
Load Byte
Load Byte Unsigned
Load Halfword
Load Halfword Unsigned
Load Word
Load Word Left
SB
SH
SW
SWL
SWR
SYNC
LWR
Load Word Right
Arithmetic Instructions: ALU Immediate
ADDI
ADDIU
ANDI
Add Immediate
Add Immediate Unsigned
AND Immediate
ORI
SLTI
SLTIU
LUI Load Upper Immediate
XORI
Arithmetic Instructions: Three-Operand, Register-Type
ADD
ADDU
AND
NOR
OR
Add
Add Unsigned
Logical AND
Logical NOR
Logical OR
SLT
SLTU
SUB
SUBU
XOR
(Sheet 1 of 4)
Store Byte
Store Halfword
Store Word
Store Word Left
Store Word Right
Synchronize (load/store
synchronization)
OR Immediate
Set on Less Than Immediate
Set on Less Than Immediate
Unsigned
Exclusive OR Immediate
Set on Less Than
Set on Less Than Unsigned
Subtract
Subtract Unsigned
Logical Exclusive OR
TinyRISC LR4102 Microprocessor
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L9A0212 arduino
LR4102 Register Map
Table 4
Table 4 shows the LR4102 microprocessor register memory map.
LR4102 Register Memory Map
Register Name Physical Address Description
System configuration registers in BBCC
SCR1
0x1FFF.0000
System Configuration Register 1
SCR2
0x1FFF.0004
System Configuration Register 2
SCR3
0x1FFF.0008
System Configuration Register 3
Timer registers
T0ICR
0x1FFF.0100
Timer 0 Initial Count Register
T0CCR
0x1FFF.0104
Timer 0 Current Count Register
T1ICR
0x1FFF.0108
Timer 1 Initial Count Register
T1CCR
0x1FFF.010C
Timer 1 Current Count Register
TMR
0x1FFF.0110
Mode Register
TISR
0x1FFF.0114
Interrupt Status Register
SerialICE-1 Port (UART) registers
RxStatus
RxSetup
RxData
TxStatus
TxData
0x1FFF.0200
0x1FFF.0200
0x1FFF.0204
0x1FFF.0208
0x1FFF.020C
Reserved registers
Receive (Rx) Status Register (Reading)
Receive (Rx) Setup Register (Writing)
Receive (Rx) Data Register
Transmit (Tx) Status Register
Transmit (Tx) Data Register
Reserved
0x1FFF.0300–.03FF Reserved for LSI Logic use
FBus registers
FACFG0
FACFG1
0x1FFF.0400
0x1FFF.0404
Configuration for address range 0
Configuration for address range 1
(Sheet 1 of 2)
TinyRISC LR4102 Microprocessor
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