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PDF L6911E Data sheet ( Hoja de datos )
| Número de pieza | L6911E | |
| Descripción | 5 BIT PROGRAMMABLE STEP DOWN CONTROLLER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de L6911E (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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L6911E
5 BIT PROGRAMMABLE STEP DOWN CONTROLLER
WITH SYNCHRONOUS RECTIFICATION
www.DataSheet4U.com
s OPERATING SUPPLY IC VOLTAGE FROM 5V
TO 12V BUSES
s UP TO 1.3A GATE CURRENT CAPABILITY
s TTL-COMPATIBLE 5 BIT PROGRAMMABLE
OUTPUT COMPLIANT WITH VRM 8.5 :
1.050V TO 1.825V WITH 0.025V BINARY
STEPS
s VOLTAGE MODE PWM CONTROL
s EXCELLENT OUTPUT ACCURACY: ±1%
OVER LINE AND TEMPERATURE
VARIATIONS
s VERY FAST LOAD TRANSIENT RESPONSE:
FROM 0% TO 100% DUTY CYCLE
s POWER GOOD OUTPUT VOLTAGE
s OVERVOLTAGE PROTECTION AND
MONITOR
s OVERCURRENT PROTECTION REALIZED
USING THE UPPER MOSFET’S RdsON
s 200KHz INTERNAL OSCILLATOR
s OSCILLATOR EXTERNALLY ADJUSTABLE
FROM 50KHz TO 1MHz
s SOFT START AND INHIBIT FUNCTIONS
APPLICATIONS
s POWER SUPPLY FOR ADVANCED
MICROPROCESSOR CORE
s DISTRIBUTED POWER SUPPLY
BLOCK DIAGRAM
Vcc 5V to12V
November 2001
PGOOD
SS
OVP
RT
VD0
VD1
VD2
VD3
VD4
VCC
OCSET
MONITOR and
PROTECTION
OSC
D/A
+
-
+
PWM
-
E/A
D98IN957
COMP
SO-20
ORDERING NUMBERS: L6911E
L6911ETR (Tape and Reel)
DESCRIPTION
The device is a power supply controller specifically
designed to provide a high performance DC/DC con-
version for high current microprocessors. A precise 5
bit digital to analog converter (DAC) allows to adjust
the output voltage from 1.050 to 1.825 with 25mV bi-
nary steps.
The high precision internal reference assures the se-
lected output voltage to be within ±1%. The high peak
current gate drive affords to have fast switching to the
external power mos providing low switching losses.
The device assures a fast protection against load
overcurrent and load over-voltage. An external SCR
is triggered to crowbar the input supply in case of
hard overvoltage. An internal crowbar is also provid-
ed turning on the low side mosfet as long as the over-
voltage is detected. In case of over-current detection,
the soft start capacitor is discharged an the system
works in HICCUP mode.
BOOT
UGATE
PHASE
LGATE
PGND
GND
VSEN
VFB
Vin 5V to12V
Vo
1.050V to 1.825V
1/20
1 page  
L6911E
Table 1. VID Setting
VID4
(25mV)
VID3
VID2
0 01
1 01
0 00
1 00
0 00
1 00
0 00
1 00
0 00
1 00
0 11
1 11
0 11
1 11
0 11
1 11
VID1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
VID0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Outp ut
Voltage (V)
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
VID4
(25mV)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VID3
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
VID2 VID1
10
10
01
01
01
01
00
00
00
00
11
11
11
11
10
10
VID0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Outpu t
Voltage (V)
1.450
1.475
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.775
1.800
1.825
Device Description
The device is an integrated circuit realized in BCD technology. It provides complete control logic and protections
for a high performance step-down DC-DC converter optimized for microprocessor power supply. It is designed
to drive N Channel Mosfets in a synchronous-rectified buck topology. The device works properly with Vcc rang-
ing from 5V to 12V and regulates the output voltage starting from a 1.26V power stage supply voltage (Vin). The
output voltage of the converter can be precisely regulated, programming the VID pins, from 1.050V to 1.825V
with 25mV binary steps, with a maximum tolerance of ±1% over temperature and line voltage variations. The
device provides voltage-mode control with fast transient response. It includes a 200kHz free-running oscillator
that is adjustable from 50kHz to 1MHz. The error amplifier features a 15MHz gain-bandwidth product and 10V/
ms slew rate which permits high converter bandwidth for fast transient performance. The resulting PWM duty
cycle ranges from 0% to 100%. The device protects against over-current conditions entering in HICCUP mode.
The device monitors the current by using the rDS(ON) of the upper MOSFET which eliminates the need for a cur-
rent sensing resistor.
The device is available in SO20 package.
Oscillator
The switching frequency is internally fixed to 200kHz. The internal oscillator generates the triangular waveform
for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the
oscillator is tipically 50µA (Fsw=200KHz) and may be varied using an external resistor (RT) connected between
RT pin and GND or VCC. Since the RT pin is maintained at fixed voltage (typ. 1.235V), the frequency is varied
proportionally to the current sinked (forced) from (into) the pin.
In particular connecting it to GND the frequency is increased (current is sinked from the pin), according to the
following relationship:
fS = 200kH z + -4--R-.--9-T--4--(--k-⋅---1Ω---0--)--6-
Connecting RT to VCC=12V or to VCC=5V the frequency is reduced (current is forced into the pin), according
to the following relationships:
5/20
5 Page 
Figure 6. Output transient response without (a) and with (b) the droop function
ESR DROP
ESR DROP
L6911E
VNOM
VMAX
VMIN
VDROOP
(a) (b)
As shown in figure 6, the ESR drop is present in any case, but using the droop function the total deviation of the
output voltage is minimized. In practice the droop function introduces a static error (Vdroop in figure 6) propor-
tional to the output current. Since a sense resistor is not present, the output DC current is measured by using
the intrinsic resistance of the inductance (a few mΩ). So the low-pass filtered inductor voltage (that is the induc-
tor current) is added to the feedback signal, implementing the droop function in a simple way. Referring to the
schematic in figure 7, the static characteristic of the closed loop system is:
VOUT
=
VPROG
+
VPROG
⋅
R-----3-----+-----R-----8------/--/---R-----9-
R2
–
R-----L----⋅---R--R---8--8----/--/---R-----9--⋅
IOUT
Where VPROG is the output voltage of the digital to analog converter (i.e. the set point) and RL is the inductance
resistance. The second term of the equation allows a positive offset at zero load (∆V+); the third term introduces
the droop effect (∆VDROOP). Note that the droop effect is equal the ESR drop if:
R-----L----⋅---R-----8-------/-/----R-----9- = ESR
R8
Figure 7. Compensation network
VIN
V C OM P
C 18
ZF
V P RO G
PW M
C 20
R4
R3
R2
VP HA SE
L2 RL
R8
R9
C 25
ZI
VO UT
E SR
C 6-15
Considering the previous relationships R2, R3, R8 and R9 may be determined in order to obtain the desired
droop effect as follow:
s Choose a value for R2 in the range of hundreds of KΩ to obtain realistic values for the other
components.
11/20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet L6911E.PDF ] | |
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