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PDF IA188EM Datasheet ( Hoja de datos )

Número de pieza IA188EM
Descripción (IA186EM / IA188EM) 8/16-Bit Microcontrollers
Fabricantes InnovASIC 
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IA188EM datasheet

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IA188EM pdf
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Description
The IA186EM/188EM family of microcontrollers replaces obsolete AMD# Am186EM/188EM devices,
allowing customers to retain existing board designs, software compilers/assemblers and emulation tools,
thereby avoiding expensive redesign efforts.
The IA186EM/188EM microcontrollers are an upgrade for the 80C186/188 microcontroller designs, with
integrated peripherals to provide increased functionality and reduce system costs. The Innovasic devices
are created to satisfy requirements of embedded products designed for telecommunications, office
automation and storage and industrial controls.
A block diagram of the IA186EM/188EM microcontroller is depicted in Figure 1. The IA186EM/188EM
microcontroller consists of the following functional blocks, with brief discussions of each afterwards.
" Bus Interface and Control
" Peripheral Control and Registers
" Chip Selects and Control
" Programmable I/O
" Clock and Power Management
" Direct Memory Access (DMA)
" Interrupt Controller
" Timers
" Asynchronous Serial Ports
" Synchronous Serial Interface.
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com

5 Page

IA188EM arduino
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
PRL Value
01h
02h
03h
04h
Processor Release Level
C
D
E
F
RES (bits 7-0) – Reserved.
PDCON (0f0h) - The Power-save CONtrol Register controls several miscellaneous system I/O and
timing functions.
The SYSCON contains 0000h at reset.
15 14
13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSEN RES CBF CBD CAF CAD RES F2 F1 F0
PSEN (bit 15) – When set to 1, enables the power-save mode causing the internal operating clock to
be divided by the value in F2-F0. External interrupts or interrupts from internal interrupts
automatically clear PSEN. Software interrupts and exception do not clear PSEN. Note that the value of
PSEN is not restored upon execution of an IRET instruction.
RES (bit 14-12) – Reserved. These bits read back as zeros.
CBF (bit 11) – When set to 1, the clkoutb output follows the input crystal (PLL) frequency. When
this bit is 0, the clkoutb follows the internal clock frequency after the clock divider.
CBD (bit 10) – When set to 1, the clkoutb output is pulled low. When this bit is 0, the clkoutb is
driven as an output per the CBF bit.
CAF (bit 9) – When set to 1, the clkouta output follows the input crystal (PLL) frequency. When this
bit is 0, the clkouta follows the internal clock frequency after the clock divider.
CAD (bit 8) – When set to 1, the clkouta output is pulled low. When this bit is 0, the clkouta is driven
as an output per the CBF bit.
RES (bits 7-3) – Reserved. These bits read back as zeros.
F2-F0 (bits 2-0) – These bits control the clock divider as shown below. Note that PSEN must be 1 for
the clock divider to function.
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com

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