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PDF IA188EM Datasheet ( Hoja de datos )

Número de pieza IA188EM
Descripción (IA186EM / IA188EM) 8/16-Bit Microcontrollers
Fabricantes InnovASIC 
Logotipo InnovASIC Logotipo

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IA188EM Hoja de datos, Descripción, Manual
IA186EM/IA188EM
8/16-Bit Microcontrollers
Data Sheet
www.DataSheet4U.com
Copyright ! 2004

1 page

IA188EM pdf
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Description
The IA186EM/188EM family of microcontrollers replaces obsolete AMD# Am186EM/188EM devices,
allowing customers to retain existing board designs, software compilers/assemblers and emulation tools,
thereby avoiding expensive redesign efforts.
The IA186EM/188EM microcontrollers are an upgrade for the 80C186/188 microcontroller designs, with
integrated peripherals to provide increased functionality and reduce system costs. The Innovasic devices
are created to satisfy requirements of embedded products designed for telecommunications, office
automation and storage and industrial controls.
A block diagram of the IA186EM/188EM microcontroller is depicted in Figure 1. The IA186EM/188EM
microcontroller consists of the following functional blocks, with brief discussions of each afterwards.
" Bus Interface and Control
" Peripheral Control and Registers
" Chip Selects and Control
" Programmable I/O
" Clock and Power Management
" Direct Memory Access (DMA)
" Interrupt Controller
" Timers
" Asynchronous Serial Ports
" Synchronous Serial Interface.
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com

5 Page

IA188EM arduino
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
F2 F1 F0 Divider Factor
0 0 0 Divide by 1 (20)
0 0 1 Divide by 2 (21)
0 1 0 Divide by 4 (22)
0 1 1 Divide by 8 (23)
1 0 0 Divide by 16 (24)
1 0 1 Divide by 32 (25)
1 1 0 Divide by 64 (26)
1 1 1 Divide by 128 (27)
EDRAM (0e4h) - The Enable RCU Register provides control and status for the refresh counter.
The EDRAM register contains 0000h at reset.
15 14 13 12 11 10
9 8 76543 2 1
E0 0 0 0 0 0
T [8:0]
0
E (bit 15) – When set to 1, the refresh counter is enabled and msc3_n is configured to act as rfsh_n.
Clearing E clears the refresh counter and disables refresh requests. The refresh address is unaffected
by clearing E.
RES (bits 14-9) – Reserved. These bits read back as 0.
T [8:0] (bits 8-0) – These bits hold the current value of the refresh counter. These bits are read-only.
CDRAM (0e2h) - The Clock Prescaler Register determines the period between refresh cycles.
The CDRAM register is undefined at reset.
15 14 13 12 11 10
9 8 76543 2 1
00 0 0 0 0 0
RC [8:0]
0
RES (bits 15-9) – Reserved. These bits read back as 0.
RC [8:0] (bits 8-0) – These bits hold the clock count interval between refresh cycles. This value
should not be set to less than 18 (12h), else there would never be sufficient bus cycles available for the
processor to execute code.
In power-save mode, the refresh counter value should be adjusted to account for the clock divider
value in SYSCON.
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com

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