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Número de pieza OPAMP3EVB
Descripción Op Amp Evaluation Board Manual
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OPAMP3EVB
Op Amp Evaluation
Board Manual
TSSOP−16 Package
Description
This document describes the TSSOP−16 package Op
Amp evaluation board. It should be used in conjunction with
the appropriate data sheet which contains full technical
details on the device specification and operation. This
evaluation board is offered as a convenience for the
customers interested in performing their own engineering
characterization and performance assessment. The
evaluation board provides a 50 W controlled impedance
environment. The evaluation board is designed to facilitate
a quick evaluation of the device. The populated evaluation
board will have a gain of two in a non−inverting op amp
configuration.
This evaluation board manual contains:
Information on NCS2530DTBEVB Evaluation Board
www.DataSheet4U.com
for NCS2530 Op Amp
http://onsemi.com
Information on NCS2535DTBEVB Evaluation Board
for NCS2535 Op Amp
Information on NCS2540DTBEVB Evaluation Board
for NCS2540 Op Amp
Bill of Materials
Board Lay−up
The TSSOP−16 evaluation boards are implemented in
two layers (Figure 1, Evaluation Board Lay−up). The first
layer is the 1.0 oz copper ground plane, where a portion of
the ground plane is cut out to mount the device. The FR4
dielectric material is placed between the first and second
layer. The second layer contains the rest of the components
and primary signal traces.
Top Silkscreen
Top Soldermask
Top Plating
01 Cu = 1 Oz, 0.0014
Top Metal
Adjust
02
Tw = 0.045, Zo = 50 W, Cu = 1 Oz, 0.0014
Bottom Metal
Bottom Plating
Bottom Soldermask
Bottom Silkscreen
Figure 1. Evaluation Board Lay−up
Board Design (NCS2530DTBEVB/NCS2535DTBEVB)
The evaluation board was designed for non−inverting op
amp configuration (See Figure 2). The input contains
termination resistor (usually 50 W). The input can also be
monitored through J1, J4, and J7. The evaluation board has
versatile loading options for the op amp, depending on the
user’s preference, it can be configured as capacitive load,
series resistance load, parallel resistance load, etc.
© Semiconductor Components Industries, LLC, 2005
September, 2005 − Rev. 0
1
Publication Order Number:
OPAMP3EVB/D

1 page




OPAMP3EVB pdf
OPAMP3EVB
Board Design (NCS2540DTBEVB)
The evaluation board was designed for non−inverting op
amp configuration (See Figure 5). The input contains
termination resistor (usually 50 W). The input can also be
monitored through J1, J4, and J7. The evaluation board has
versatile loading options for the op amp, depending on the
user’s preference, it can be configured as capacitive load,
series resistance load, parallel resistance load, etc.
VCC OA Ferrite Bead
Banana Jack L2
J10
GND
Banana Jack
11, 13, 16 J12
3, 6, 9
Ferrite Bead VEE OA
L1 Banana Jack
J11
D6 C7 C6 C5 C8 C12
R7
C1 C4 C3 C2 C
R5
D7
BNC Connector
Scope
+IN1
J1
R1
R2
BNC Connector
+IN1
J2
R3
BNC Connector
Scope
+IN2
J4
R8
R9
BNC Connector
+IN2
J5
R18
EN1
JMP1
VCC
VEE
2+
14
15
1
R6
R4
R10
C9
BNC Connector
Out
R11 J3
EN2
JMP2
VCC
VEE
5+
13
12
4
R17
R15
R12
C10
BNC Connector
Out2
R13 J6
Figure 5. NCS2540 Evaluation Board Schematic
http://onsemi.com
5

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OPAMP3EVB arduino
Notes
OPAMP3EVB
http://onsemi.com
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