PDF K7I641882M Data sheet ( Hoja de datos )

Número de pieza	K7I641882M
Descripción	(K7I643682M / K7I641882M) 72Mb M-die DDRII SRAM Specification 165 FBGA
Fabricantes	Samsung semiconductor
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No Preview Available ! K7I643682M K7I641882M 2Mx36 & 4Mx18 DDRII CIO b2 SRAM 72Mb M-die DDRII SRAM Specification 165 FBGA with Pb & Pb-Free (RoHS compliant) www.DataSheet4U.com INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi- lar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. - 1 - Aug. 2005 Rev 1.0 1 page K7I643682M K7I641882M 2Mx36 & 4Mx18 DDRII CIO b2 SRAM PIN CONFIGURATIONS(TOP VIEW) K7I641882M(4Mx18) 123456 A CQ SA SA R/W BW1 K B NC DQ9 NC SA NC K C NC NC NC VSS SA SA0 D NC NC DQ10 VSS VSS VSS E NC NC DQ11 VDDQ VSS VSS F NC DQ12 NC VDDQ VDD VSS G NC NC DQ13 VDDQ VDD VSS H Doff VREF VDDQ VDDQ VDD VSS J NC NC NC VDDQ VDD VSS K NC NC DQ14 VDDQ VDD VSS L NC DQ15 NC VDDQ VSS VSS M NC NC NC VSS VSS VSS N NC NC DQ16 VSS SA SA P NC NC DQ17 SA SA C R TDO TCK SA SA SA C Notes: 1. BW0 controls write to DQ0:DQ8 and BW1 controls write to DQ9:DQ17. 7 NC BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC DQ7 NC NC NC NC VREF DQ4 NC NC DQ1 NC NC TMS 11 CQ DQ8 NC NC DQ6 DQ5 NC ZQ NC DQ3 DQ2 NC NC DQ0 TDI PIN NAME SYMBOL K, K C, C CQ, CQ Doff SA0 SA DQ0-17 R/W LD BW0, BW1 VREF ZQ VDD VDDQ VSS TMS TDI TCK TDO NC PIN NUMBERS 6B, 6A 6P, 6R 11A, 1A 1H 6C 2A,3A,9A,10A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R 2B,11B,10C,3D,3E,11E,2F,11F,3G,10J,3K,11K,2L,11L 10M,3N,3P,11P 4A 8A 7B, 5A 2H,10H 11H 5F,7F,5G,7G,5H,7H,5J,7J,5K,7K 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L 4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N 10R 11R 2R 1R 7A,1B,3B,5B,9B,10B,1C,2C,3C,9C,11C,1D,2D,9D,10D,11D 1E,2E,9E,10E,1F,3F,9F,10F,1G,2G,9G,10G,11G 1J,2J,3J,9J,11J,1K,2K,9K,10K,1L,3L,9L,10L 1M,2M,3M,9M,11M,1N,2N,9N,10N,11N,1P,2P,9P,10P DESCRIPTION Input Clock Input Clock for Output Data Output Echo Clock DLL Disable when low Burst Count Address Inputs Address Inputs NOTE 1 Data Inputs Outputs Read, Write Control Pin, Read active when high Synchronous Load Pin, bus Cycle sequence is to be defined when low Block Write Control Pin,active when low Input Reference Voltage Output Driver Impedance Control Input Power Supply ( 1.8 V ) Output Power Supply ( 1.5V or 1.8V ) Ground JTAG Test Mode Select JTAG Test Data Input JTAG Test Clock JTAG Test Data Output 2 No Connect 3 Notes: 1. C, C, K or K cannot be set to VREF voltage. 2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected. 3. Not connected to chip pad internally. - 5 - Aug. 2005 Rev 1.0 5 Page K7I643682M K7I641882M 2Mx36 & 4Mx18 DDRII CIO b2 SRAM THERMAL RESISTANCE PRMETER SYMBOL Typ Unit NOTES Junction to Ambient θJA 21 °C/W Junction to Case θJC 2.48 °C/W Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site thermal impedance. TJ=TA + PD x θJA PIN CAPACITANCE PRMETER Address Control Input Capacitance Input and Output Capacitance Clock Capacitance SYMBOL CIN COUT CCLK Note: 1. Parameters are tested with RQ=250Ω and VDDQ=1.5V. 2. Periodically sampled and not 100% tested. AC TEST CONDITIONS Parameter Sym- Value Core Power Supply Voltage Output Power Supply Voltage Input High/Low Level Input Reference Level Input Rise/Fall Time Output Timing Reference Level VDD VDDQ VIH/ VREF TR/TF 1.7~1.9 1.4~1.9 1.25/0.25 0.75 0.3/0.3 VDDQ/2 Note: Parameters are tested with RQ=250Ω Overershoot Timing TESTCONDITION VIN=0V VOUT=0V - TYP 3.5 4 3 MAX 4 5 4 Unit pF pF pF NOTES AC TEST OUTPUT LOAD Unit V VREF 0.75V VDDQ/2 V V SRAM Zo=50Ω 50Ω V ns 250Ω ZQ V Undershoot Timing VDDQ+0.5V VDDQ+0.25V VDDQ 20% tKHKH(MIN) VIH VSS VSS-0.25V VSS-0.5V VIL Note: For power-up, VIH ≤ VDDQ+0.3V and VDD ≤ 1.7V and VDDQ ≤ 1.4V t ≤ 200ms 20% tKHKH(MIN) - 11 - Aug. 2005 Rev 1.0 11 Page

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