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PDF IR5001 Data sheet ( Hoja de datos )
| Número de pieza | IR5001 | |
| Descripción | UNIVERSAL ACTIVE ORING CONTROLLER | |
| Fabricantes | International Rectifier | |
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Data Sheet No.PD60229
IR5001
UNIVERSAL ACTIVE ORING CONTROLLER
DESCRIPTION
The IR5001 is a universal high-speed controller and
N-channel power MOSFET driver for Active ORing and
reverse polarity protection applications. The output voltage
of the IR5001 is determined based on the polarity of the
voltage difference on its input terminals. In particular, if the
current flow through an N-channel ORing FET is from
source to drain, the output of the IR5001 will be pulled
high to Vcc, thus turning the Active ORing FET on. If the
current reverses direction and flows from drain to source
(due to a short-circuit failure of the source, for example),
the IC will quickly switch the Active ORing FET off. Typical
turn-off delay for the IR5001 is only 130nS, which helps to
minimize voltage sags on the redundant dc voltage.
Both inputs to the IC (INN and INP) as well as Vline
input contain integrated high voltage resistors and internal
clamps. This makes the IR5001 suitable for applications at
voltages up to 100V, and with a minimum number of
external components.
FEATURES
Controller / driver IC in an SO-8 package for
implementation of Active ORing / reverse polarity
protection using N-channel Power MOSFETs
Suitable for both input ORing (for carrier class
telecom equipment) as well as output ORing for
redundant DC-DC and AC-DC power supplies
130ns Typical Turn-Off delay time
3A Peak Turn-Off gate drive current
Asymmetrical offset voltage of the internal high-speed
comparator prevents potential oscillations at light load
Ability to withstand continuous gate short conditions
Integrated voltage clamps on both comparator inputs
allow continuous application of up to 100V
Option to be powered either directly from 36-75V
universal telecom bus (100V max), or from an
external bias supply and bias resistor
Input/Output pins to determine the state of the Active
ORing circuit and power system redundancy
APPLICATIONS
-48V/-24V Input Active ORing for carrier class communication equipment
Reverse input polarity protection for DC-DC power supplies
24V/48V output active ORing for redundant AC-DC rectifiers
Low output voltage (12V, 5V, 3.3V...) active ORing for redundant DC-DC and AC-DC power supplies
Active ORing of multiple voltage regulators for redundant processor power
TYPICAL APPLICATION
+48V input A
B
FET Check Pulse
FET A Status
IR5001
Vline Vout
Vcc Gnd
FETch INN
FETst INP
-48V input A
Fet B Status
IR5001
Vline Vout
Vcc Gnd
FETch INN
FETst INP
DC
DC
-48V input B
Figure 1 - Typical application of the IR5001 in - 48V input,
carrier class telecommunications equipment.
www.irf.com
PACKAGE / ORDERING
INFORMATION
Top View
Vline 1
Vcc 2
FETch 3
FETst 4
8 Vout
7 Gnd
6 INN
5 INP
θJA=128°C/W
Ordering P/N Package
IR5001S 8 - Pin SOIC
1
1 page  
PARAMETER DEFINITION AND TIMING DIAGRAM
IR5001
VOUT
VOUT
(0,0)
VOS
VHYST
VINP - VINN
Figure 3 - Input Comparator Offset (Vos ) and Hysteresis
Voltage (Vhyst) Definition.
-Vos
Gnd
VHYST
VINN
(VINP=Gnd)
Figure 4 - Input Comparator Hysteresis Definition.
90mV
50mV
0
VIN
(VINP - VINN)
10ns
VINP - VINN = 200mV
td(on)
90%
10ns
-50mV
-90mV
VOH
td(off)
50%
VOUT
VOL 10%
tr
Figure 5 - Dynamic Parameters.
tf
www.irf.com
5
5 Page 
IR5001
In a well - designed Active ORing circuit, the
Rds(on) of the Active ORing FET should generate
between 50mV to 100mV of (INP – INN) voltage
during normal, steady state operation. (The normal
operation refers to current flowing from the source to
drain of the Active ORing FET, half of the full-load
system current flowing through each OR-ed source,
at nominal input voltage). Maximum power
dissipation under worst-case conditions for the FET
should be calculated and verified against the data
sheet limits of the selected device.
IR5001 Thermal considerations
Maximum junction temperature of the IR5001 in an
application should not exceed the maximum
operating junction temperature, specified at 125°C:
Tj = Pdiss * Rtheta j-a + Tamb <= Tj (max),
where Rtheta j-a is the thermal resistance from
junction to ambient thermal resistance (specified at
128 °C/W), Pdiss is IC power dissipation, and Tamb
is operating ambient temperature.
The maximum power dissipation can be estimated
as follows:
Pdiss < (Tj max – Tamb max) / Rtheta j-a
Since Tj max= 125 °C, Tamb = 85 °C, and Rtheta j-a
= 128 °C/W, the maximum power dissipation allowed
is:
Pdiss max = (125 – 85) / 128 = 0.3W
With proper selection of Icc (as discussed in the
Detailed Pin Description), the maximum power
dissipation will never be exceeded (Max Icc * Max
Vcc = 10mA * 13.9V = 0.14W).
Layout Considerations
INN and INP should be connected very close to
the drain and source terminal of the Active ORing
FET. PCB trace between the Vout pin and the gate
of the N-FET should also be minimized. A minimum
of 0.1uF decoupling capacitor must be connected
from Vcc to Gnd of the IR5001and should be placed
as close to the IR5001 as possible. Ground should
be connected to the source of N-FET separately
from the INP pin.
www.irf.com
11
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| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet IR5001.PDF ] | |
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