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PDF P2040A Data sheet ( Hoja de datos )
| Número de pieza | P2040A | |
| Descripción | LCD Panel EMI Reduction IC | |
| Fabricantes | Alliance Semiconductor | |
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October 2005
rev 1.2
LCD Panel EMI Reduction IC
P2040A
Features
www.DataSheet4U.com
FCC approved method of EMI attenuation.
Provides up to 20dB of EMI suppression.
Generates a low EMI spread spectrum clock of the
input frequency.
Input frequency range: 30MHz to 100MHz.
Optimized for VGA, SVGA, and higher resolution
XGA LCD Panels.
Internal loop filter minimizes external components
and board space.
Six selectable high spread ranges up to ± 2%.
Two selectable modulation rates.
SSON# control pin for spread spectrum enable and
disable options.
Low cycle-to-cycle jitter.
Wide operating range.
Low power CMOS design.
Supports most mobile graphic accelerator
specifications.
Products available for automotive temperature
range. (Refer Spread Spectrum Range Selection
Tables)
Available in 8-pin SOIC and TSSOP Packages.
Product Description
The P2040A is a versatile spread spectrum frequency
modulator designed specifically for digital flat panel
applications. The P2040A reduces electromagnetic
interference (EMI) at the clock source, allowing system
wide reduction of EMI of down stream clock and data
dependent signals. The P2040A allows significant system
cost savings by reducing the number of circuit board
layers ferrite beads, shielding and other passive
components that are traditionally required to pass EMI
regulations.
The P2040A uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented in a proprietary all digital method.
The P2040A modulates the output of a single PLL in
order to “spread” the bandwidth of a synthesized clock,
and more importantly, decreases the peak amplitudes of
its harmonics. This results in significantly lower system
EMI compared to the typical narrow band signal produced
by oscillators and most frequency generators. Lowering
EMI by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation’.
Applications
The P2040A is targeted towards digital flat panel
applications for notebook PCs, palm-size PCs, office
automation equipments and LCD monitors.
Block Diagram
SR0 SR1 MRA SSON#
VDD
CLKIN
Frequency
Divider
Feedback
Divider
Modulation
Phase
Detector
Loop
Filter
PLL
VCO
Output
Divider
ModOUT
VSS
Alliance Semiconductor
2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
1 page  
October 2005
P2040A
rev 1.2
Absolute Maximum Ratings
Symbol
Parameter
VDD, VIN Voltage on any pin with respect to Ground
TSTG
Storage temperature
TC Operating temperature-Commercial
TA Operating temperature – Automotive
TJ Junction Temperature
Rating
-0.5 to +7.0
-65 to +125
0 to 70
-40 to +125
150
Unit
V
°C
°C
°C
°C
TDV Static Discharge Voltage
(As per JEDEC STD22- A114-B)
2 KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
DC Electrical Characteristics
(Test condition: All parameters are measured at room temperature (+25°C) unless otherwise stated)
Symbol
Parameter
Min
VIL Input low voltage
VSS - 0.3
VIH Input high voltage
IIL
Input low current
(pull-up resistor on inputs SR0, SR1 and MRA)
IIH Input high current (pull-down resistor on input SSON#)
2.0
-35
-
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VOL
VOH
Output low voltage (VDD = 3.3V, IOL = 20mA)
Output high voltage (VDD = 3.3V, IOH = 20mA)
-
2.5
IDD Static supply current standby mode
-
ICC Dynamic supply current (3.3V and 10pF loading)
7
VDD Operating voltage
2.7
tON Power-up time (first locked cycle after power up)
-
ZOUT Clock output impedance
-
Typ
-
-
-
-
-
-
0.6
10
3.3
0.18
50
Max
0.8
VDD + 0.3
-
35
0.4
-
-
13
3.7
-
-
Unit
V
V
µA
µA
V
V
mA
mA
V
mS
Ω
AC Electrical Characteristics
Symbol
Parameter
fIN Input frequency
fOUT Output frequency
tLH* Output rise time (measured at 0.8V to 2.0V)
tHL* Output fall time (measured at 2.0V to 0.8V)
tJC Jitter (cycle to cycle)
tD Output duty cycle
*tLH and tHL are measured into a capacitive load of 15pF
Min Typ Max Unit
30 - 100 MHz
30 - 100 MHz
0.7 0.9 1.1 nS
0.6 0.8 1.0 nS
- - 360 pS
45 50 55 %
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
5 of 9
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| PDF Descargar | [ Datasheet P2040A.PDF ] | |
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