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PDF DP83865 Data sheet ( Hoja de datos )
| Número de pieza | DP83865 | |
| Descripción | Gig PHYTER V 10/100/1000 Ethernet Physical Layer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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October 2004
DP83865 Gig PHYTER® V
10/100/1000 Ethernet Physical Layer
General Description
The DP83865 is a fully featured Physical Layer transceiver
with integrated PMD sublayers to support 10BASE-T,
100BASE-TX and 1000BASE-T Ethernet protocols.
The DP83865 is an ultra low power version of the DP83861
and DP83891. It uses advanced 0.18 um, 1.8 V CMOS
technology, fabricated at National Semiconductor’s South
Portland, Maine facility.
The DP83865 is designed for easy implementation of
10/100/1000 Mb/s Ethernet LANs. It interfaces directly to
Twisted Pair media via an external transformer. This device
interfaces directly to the MAC layer through the IEEE
802.3u Standard Media Independent Interface (MII), the
IEEE 802.3z Gigabit Media Independent Interface (GMII),
or Reduced GMII (RGMII).
The DP83865 is a fourth generation Gigabit PHY with field
proven architecture and performance. Its robust perfor-
mance ensures drop-in replacement of existing
10/100 Mbps equipment with ten to one hundred times the
performance using the existing networking infrastructure.
Applications
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The DP83865 fits applications in:
■ 10/100/1000 Mb/s capable node cards
■ Switches with 10/100/1000 Mb/s capable ports
■ High speed uplink ports (backbone)
Features
■ Ultra low power consumption typically 1.1 watt
■ Fully compliant with IEEE 802.3 10BASE-T, 100BASE-
TX and 1000BASE-T specifications
■ Integrated PMD sublayer featuring adaptive equalization
and baseline wander compensation according to ANSI
X3.T12
■ 3.3 V or 2.5 V MAC interfaces:
■ IEEE 802.3u MII
■ IEEE 802.3z GMII
■ RGMII version 1.3
■ User programmable GMII pin ordering
■ IEEE 802.3u Auto-Negotiation and Parallel Detection
■ Fully Auto-Negotiates between 1000 Mb/s, 100 Mb/s,
and 10 Mb/s full duplex and half duplex devices
■ Speed Fallback mode to achieve quality link
■ Cable length estimator
■ LED support for activity, full / half duplex, link1000,
link100 and link10, user programmable (manual on/off),
or reduced LED mode
■ Supports 25 MHz operation with crystal or oscillator.
■ Requires only two power supplies, 1.8 V (core and
analog) and 2.5 V (analog and I/O). 3.3V is supported
as an alternative supply for I/O voltage
■ User programable interrupt
■ Supports Auto-MDIX at 10, 100 and 1000 Mb/s
■ Supports JTAG (IEEE1149.1)
■ 128-pin PQFP package (14mm x 20mm)
SYSTEM DIAGRAM
DP83820
10/100/1000 Mb/s
ETHERNET MAC
MII
GMII
RGMII
DP83865
10/100/1000 Mb/s
ETHERNET PHYSICAL LAYER
10BASE-T
100BASE-TX
1000BASE-T
25 MHz
crystal or oscillator
PHYTER® is a registered trademark of National Semiconductor Corporation
© 2004 National Semiconductor Corporation
STATUS
LEDs
www.national.com
1 page  
1.0 Pin Description
The DP83865 pins are classified into the following interface
categories (each is described in the sections that follow):
— MAC Interfaces
— Management Interface
— Media Dependent Interface
— JTAG Interface
— Clock Interface
— Device Configuration and LED Interface
— Reset
— Power and Ground Pins
— Special Connect Pins
Type: I
Type: O
Type: O_Z
Type: I/O_Z
Type: S
Type: PU
Type: PD
Inputs
Output
Tristate Output
Tristate Input_Output
Strapping Pin
Internal Pull-up
Internal Pull-down
1.1 MAC Interfaces (MII, GMII, and RGMII)
Signal Name
CRS/RGMII_SEL0
Type
PQFP
Pin #
Description
O_Z, 40 CARRIER SENSE or RGMII SELECT: CRS is asserted high to indicate the
S, PD
presence of a carrier due to receive or transmit activity in Half Duplex mode.
For 10BASE-T and 100BASE-TX Full Duplex operation CRS is asserted when
a received packet is detected. This signal is not defined for 1000BASE-T Full
Duplex mode.
In RGMII mode, the CRS is not used. This pin can be used as a RGMII strap-
ping selection pin.
RGMII_SEL1 RGMII_SEL0
00
01
10
11
MAC Interface
= GMII
= GMII
= RGMII - HP
= RGMII - 3COM
COL/CLK_MAC_FREQ O_Z, 39 COLLISION DETECT: Asserted high to indicate detection of a collision condi-
S, PD
tion (assertion of CRS due to simultaneous transmit and receive activity) in
Half Duplex modes. This signal is not synchronous to either MII clock
(GTX_CLK, TX_CLK or RX_CLK). This signal is not defined and stays low for
Full Duplex modes.
CLOCK TO MAC FREQUENCY Select:
1 = CLOCK TO MAC output is 125 MHz
0 = CLOCK TO MAC output is 25 MHz
TX_CLK/RGMII_SEL1 O_Z, 60 TRANSMIT CLOCK or RGMII SELECT: TX_CLK is a continuous clock signal
S, PD
generated from reference CLK_IN and driven by the PHY during 10 Mbps or
100 Mbps MII mode. TX_CLK clocks the data or error out of the MAC layer and
into the PHY.
The TX_CLK clock frequency is 2.5 MHz in 10BASE-T and 25 MHz in
100BASE-TX mode.
Note: “TX_CLK” should not be confused with the “TX_TCLK” signal.
In RGMII mode, the TX_CLK is not used. This pin can be used as a RGMII
strapping selection pin. This pin should be pulled high for RGMII interface.
5 www.national.com
5 Page 
1.0 Pin Description (Continued)
1.8 Power and Ground Pins
(See section “5.3 Power Supply Decoupling” on page 64.)
Signal Name
IO_VDD
CORE_VDD
2V5_AVDD1
2V5_AVDD2
1V8_AVDD1
1V8_AVDD2
1V8_AVDD3
VSS
PQFP Pin #
Description
4, 15, 21, 29, 37, 42, 53, 58, 69, 2.5V or 3.3V I/O Supply for “MAC Interfaces”, “Management
77, 83, 90
Interface”, “JTAG Interface”, “Clock Interface”, “Device Con-
figuration and LED Interface” and “Reset”.
11, 19, 25, 35, 48, 63, 73, 92 1.8V Digital Core Supply
101 2.5V Analog Supply
96 2.5V Analog Supply
103, 105, 111, 117, 123
1.8V Analog Supply
98 1.8V Analog Supply - See section “5.4 Sensitive Supply
Pins” on page 64 for low pass filter recommendation.
100 1.8V Analog Supply - See section “5.4 Sensitive Supply
Pins” on page 64 for low pass filter recommendation.
5, 12, 16, 20, 22, 26, 30, 36, 38, Ground
43, 49, 54, 59, 64, 70, 74, 78, 82,
91, 93, 97, 99, 104, 106, 107,
110, 112, 113, 116, 118, 119,
122, 124, 125, 128
1.9 Special Connect Pins
Signal Name
BG_REF
RESERVED
TYPE
PQFP
Pin #
Description
I 102 Internal Reference Bias: See section “5.4 Sensitive Supply Pins” on page 64
for information on how to terminate this pin.
2, 23, These pins are reserved and must be left floating.
84
11 www.national.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DP83865.PDF ] | |
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