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Número de pieza DP83858
Descripción 100 Mb/s TX/T4 Repeater Interface Controller
Fabricantes National Semiconductor 
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No Preview Available ! DP83858 Hoja de datos, Descripción, Manual

June 1998
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DP83858
100 Mb/s TX/T4 Repeater Interface Controller (100RIC8)
General Description
The DP83858 100 Mb/s TX/T4 Repeater Interface Control-
ler, known as 100RIC8, is designed specifically to meet the
needs of today's high speed Ethernet networking systems.
The DP83858 is fully compatible with the IEEE 802.3
repeater's clause 27. This device is targeted at low port
count managed and unmanaged repeater applications.
The DP83858 supports up to eight 100 Mb/s links with its
network interface ports. The 100RIC8 can be configured to
be used with either 100BASE-TX or 100BASE-T4 PHY
technologies. Larger repeaters may be constructed by
cascading DP83858s together using the built-in Inter
Repeater bus.
In conjunction with a DP83856 100 Mb/s Repeater Infor-
mation Base device, a DP83858 based repeater becomes
a managed entity that is compatible with IEEE 802.3u
(clause 30), collecting and providing an easy interface to
all the required network statistics.
Features
s IEEE 802.3u repeater and management compatible
s Supports Class II TX translational repeater and Class I
T4 repeater
s Supports 8 network connections (ports)
s Up to 31 repeater chips cascadable for larger hub appli-
cations--may use DP83858 in conjunction with DP83850
100RIC (12 ports per chip)
s Separate jabber and partition state machines for each
port
s Management interface to DP83856 allows all repeater
MIBs to be maintained
s Large per-port management counters - reduces man-
agement CPU overhead
s On-chip elasticity buffer for PHY signal re-timing to the
DP83858 clock source
s Serial register interface - reduces cost
s Physical layer device control/status access available via
the serial register interface
s Detects repeater identification errors
s 132 pin PQFP package
System Diagram
DP83858
100 Mb/s
Repeater Interface Controller
(100RIC8)
DP83856
100 Mb/s
Repeater Information Base
(100RIB)
Inter Repeater Bus
Management Bus
RX Enable [7..0]
MII
DP83840A
100 PHY
#0
100Mb/s
Ethernet
Ports
DP83223
100BASE-X
Transceiver
Port 0
DP83840A
100 PHY
#1
DP83223
100BASE-X
Transceiver
Port 1
DP83840A
100 PHY
#2
DP83223
100BASE-X
Transceiver
Port 2
(IR_COL, IR_DV)
DP83840A
100 PHY
#7
DP83223
100BASE-X
Transceiver
Port 7
Statistics
SRAM
Management
CPU
Program
Memory
Management
I/O Devices
Note: The above system diagram depicts the repeater configured in 100BASE-TX mode.
FAST® is a registered trademark of Fairchild Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
100RICis a trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
http:\\www.national.com

1 page




DP83858 pdf
1.1 Pin Table
Pin Name
/ACTIVEO
/IR_ACTIVE
/IR_BUS_EN
/IR_COL_IN
/IR_COL_OUT
/IRD_ER
/IRD_V
/M_DV
/M_ER
/RST
/SDV
BRDC
CRS[7:0]
EE_CK
EE_CS
EE_DI
EE_DO
GND
GRDIO
IR_VECT[4:0]
IRD[3:0]
IRD_CK
IRD_ODIR
LCK
M_CK
MD[3:0]
MODE[1:0]
PART[5:0]
RDC
RDIO
RDIR
RID[4:0]
RID_ER
RSM[2:0]
RSM[3]/ RXECONFIG
RX_DV
RX_ER
RXC
RXD[3:0]
RXE[7:0]
TX_ER
TX_RDY
TXD[3:0]
TXE[7:0]
VCC
Pin No.
110
132
113
130
131
19
15
116
114
103
109
104
37-30
79
78
81
80
1, 8, 16, 28, 46, 56, 66,76, 85, 94, 101, 111, 117,123
105
125-129
14-11
10
18
100
115
119-122
83-82
84, 87-91
106
107
108
93, 96-99
92
74-72
20
25
26
27
24-21
51-48, 45-42
7
75
3-6
65-58
2, 9, 17, 29, 47, 57, 67, 77, 86, 95, 102, 112, 118, 124
5
Section
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.4
2.2
2.4
2.1
2.3
2.3
2.3
2.3
N/A
2.4
2.2
2.2
2.2
2.4
2.4
2.2
2.2
2.4
2.4
2.2
2.2
2.4
2.4
2.4
2.4
2.4
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
N/A
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DP83858 arduino
amble is being transmitted, the EB monitors the received
clock and data signals. When the start of the frame delim-
iter "SFD" is detected, the received data stream is written
into the EB. After this point, data from the EB is sent out to
the Transmit interface. The preamble is always generated
in its entirety (i.e. fifteen 5’s and one D) even if a collision
occurs.
3.5 Elasticity Buffer
The elasticity buffer, or a logical FIFO buffer, is used to
compensate for the variations and timing differences
between the recovered Receive Clock and the local clock.
This buffer supports maximum clock skews of 200 ppm for
the preamble regeneration (T4) mode, and 100 ppm for the
TX mode, within a maximum packet size of 1518 bytes.
3.6 Jabber Protection State Machine
The jabber specification for 100BASE-T is functionally dif-
ferent than 10BASE-T.
In 10BASE-T, each port's Jabber Protect State machine
ensures that Jabber transmissions are stopped after 5ms
and followed by 96 to 116 bit times silence before the port
is re-enabled.
In 100BASE-T, when a port jabbers, its receive and trans-
mit ports are cutoff until the jabber activity ceases. All other
ports remain unaffected and continue normal operation.
The 100BASE-T Jabber Protect Limit (that is, the time for
which a port can jabber until it is cutoff) for the DP83858 is
reached if the CRS is active for more than 655µs.
A jabbering port that is cut off will be re-enabled when the
jabber activity ceases and the IDLE line condition is
sensed.
3.7 Auto-Partition State Machine
In order to protect the network from a port that is experi-
encing excessive consecutive collisions, each port must
have its own auto-partition state machine.
A port with excessive consecutive collisions will be parti-
tioned after a programmed number of consecutive colli-
sions occur on that port. Transmitting ports will not be
affected.
The DP83858 has a configuration bit that allows the user to
choose how many consecutive collisions a port should
experience before partitioning. This bit can be set for
either 32 or 64 consecutive collisions. The IEEE802.3u
100BASE-T standard specifies the consecutive collisions
limit as greater than 60. A partitioned port will be recon-
nected when a collision-free packet of length 512 bits or
more (that is, at least a minimum sized packet) is transmit-
ted out of that port.
The DP83858 also provides a configuration bit that dis-
ables the auto-partition function completely.
3.8 Inter Repeater Bus Interface
The Inter Repeater bus is used to connect multiple
DP83858s together to form a logical repeater unit and also
to allow a managed entity. The IR bus allows received data
packets to be transferred from the receiving DP83858 to
the other DP83858s in the system. These DP83858s then
send the data stream to their transmit enabled ports.
Notification of collisions to other cascaded DP83858s is as
important as data transfer across the network. The arbitra-
tion logic asynchronously determines if more than one
100RIC8, cascaded together, are receiving simultaneously.
The IR bus has a set of status lines capable of conveying
collision information between DP83858s to ensure their
main state machines operate in the appropriate manner.
The IR bus consists of the following signals:
s Inter Repeater Data. This is the transfer data, in nibble
format, from the active DP83858 to all other cascaded
DP83858s.
s Inter Repeater Data Error. This signal carries the re-
ceive error status from the physical layer in real-time.
s Inter Repeater Data Valid. This signal is used to frame
good packets.
s Inter Repeater Data Clock. All IR data is synchronized
to this clock.
s Inter Repeater Data Outward Direction. This pin indi-
cates the direction of the data flow with respect to the
DP83858. When the DP83858 is driving the IR bus (i.e.
it contains port N) this signal is HIGH and when the
DP83858 is receiving data from other DP83858s over
the IR bus this signal is LOW.
s Inter Repeater Bus Enable. This signal (connected to
the /ENABLE pin of the external transceivers on the IR
bus) is used in conjunction with the IRD_ODIR signal
(connected to the DIR pin of the transceivers) to TRI-
STATE these transceivers during the change of direction
from input to output, or vice versa. This signal is always
active allowing the IR bus signals to pass through the
transceivers into or out of the 100RIC8. However when
the 100RIC8 switches from input mode (IRD_ODIR=0)
to output mode (IRD_ODIR=1), the /IR_BUS_EN signal
is deasserted allowing the transceivers to TRI-STATE
during the direction change. After this turn-around, this
signal is asserted back again. (IRD_ODIR assertion
(high) to /IR_BUS_EN low timing is a minimum of 0.1 ns.
and a maximum of 1.0. The time from /IR_BUS_EN
(high) to the IRD_ODIR high is a minimum of 10 ns. and
a maximum of 20 ns. In addition, /ACTIVEO assertion
(low) to /IR_BUS_EN high timing is a maximum of 1.0
ns.)
s Inter Repeater Activity. When there is network activity
the DP83858 asserts this output signal.
s Inter Repeater Collision Output. If there are multiple re-
ceptions on ports of a DP83858 or if the DP83858 sens-
es concurrent activity on another DP83858 it asserts this
output.
s Inter Repeater Collision Input. This input indicates that
one of the cascaded DP83858s is experiencing a colli-
sion.
s Inter Repeater Vector. When there is reception on a port
the DP83858 drives a unique vector onto these lines.
The vector on the IR bus is compared with the Repeater
ID (RID). The DP83858 will continue to drive the IR bus
if both the vector and RID match.
The following figure shows the conditions that cause an
open collector vector signal to be asserted on the back-
plane bus.
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