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PDF DP83821 Data sheet ( Hoja de datos )

Número de pieza DP83821
Descripción 10/100/1000 Mb/s PCI Ethernet Network Interface Controller
Fabricantes National Semiconductor 
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No Preview Available ! DP83821 Hoja de datos, Descripción, Manual

PRELIMINARY
February 2001
DP83821 10/100/1000 Mb/s PCI Ethernet Network Interface
Controller
www.DataSheet4U.com
General Description
DP83821 is a single-chip 10/100/1000 Mb/s Ethernet
Controller for the PCI bus. It is targeted at high-
performance adapter cards and mother boards. The
DP83821 fully implements the V2.2 33 MHz, 32-bit PCI bus
interface for host communications with power management
support. Packet descriptors and data are transferred via
bus-mastering, reducing the burden on the host CPU. The
DP83821 can support full duplex 10/100/1000 Mb/s
transmission and reception.
Features
— IEEE 802.3 Compliant, 33 Mhz, 32-bit PCI V2.2
MAC/BIU supports data rates from 1 Mb/s to 1000 Mb/s.
This allows support for traditional 10 Mb/s Ethernet, 100
Mb/s Fast Ethernet, as well as 1000 Mb/s Gigabit
Ethernet.
— Flexible, programmable Bus master - burst sizes of up to
256 dwords (1024 bytes)
— BIU compliant with PC 97 and PC 98 Hardware Design
Guides, PC 99 Hardware Design Guide draft, ACPI v1.0,
PCI Power Management Specification v1, OnNow
Device Class Power Management Reference
Specification - Network Device Class v1.0a
— Wake on LAN (WOL) support compliant with PC98,
PC99, and OnNow, including directed packets, Magic
Packet with SecureOn, ARP packets, pattern match
packets, and Phy status change
— GMII/MII provides IEEE 802.3 standard interface to
support 10/100/1000 Mb/s physical layer devices
— Ten-Bit Interface (TBI) for support of 1000BASE-X
— Virtual LAN (VLAN) and long frame support. VLAN tag
insertion support for transmit packets. VLAN tag
detection and removal for receive packets
— 802.3x Full duplex flow control, including automatic
transmission of Pause frames based on Rx FIFO
thresholds
— IPv.4 checksum task off-loading. Supports checksum
generation and verification of IP, TCP, and UDP headers
— 802.1D and 802.1Q priority queueing support. Supports
multiple priority queues in both transmit and receive
directions.
— Extremely flexible Rx packet filtration including: single
address perfect filter with MSb masking, broadcast,
2,048 entry multicast/unicast hash table, deep packet
pattern matching for up to 4 unique patterns.
— Statistics gathered for support of RFC 1213 (MIB II),
RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing
CPU overhead for management.
— Internal 8 KB Transmit and 32 KB Receive data FIFOs
— Supports Jumbo packets
— Serial EEPROM port with auto-load of configuration data
from EEPROM at power-on
— Flash/PROM interface for remote boot support
— Full Duplex support for 10/100/1000 Mb/s data rates
— 208-pin PQFP package
— Low power CMOS design
— 3.3V powered I/Os with 5V tolerant inputs
— JTAG Boundary Scan supported
System Diagram
PCI Bus
DP83821
M II
GM II
10/100/1000 M b/s
PHY
EE PR O M (optional)
Boot R O M (optional)
© 2001 National Semiconductor Corporation
www.national.com

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DP83821 pdf
2.0 Pin Descriptions (Continued)
Media Independent Interface (MII) - and Gigabit Media Independent Interface (GMII).
Symbol
RXCLK/
RXPMACLK1
RXD7,
RXD6,
RXD5,
RXD4,
RXD3,
RXD2,
RXD1,
RXD0
RXDV/RXD8
RXER/RXD9
RXEN
TXCLK/
RXPMACLK0
TXD7/MA15,
TXD6/MA14,
TXD5/MA13,
TXD4/MA12,
TXD3/MA11,
TXD2/MA10,
TXD1/MA9,
TXD0/MA8
TXEN/TXD8
Pin No(s)
156
166,
165,
164,
163,
160,
159,
158,
157
167
168
171
155
152,
151,
148,
147,
146,
145,
142,
141
153
Direction
Description
I Receive Clock: A continuous clock, sourced by an external PMD device, that is
recovered from the incoming data. During 1000 Mb/s mode RX_CLK is 125
MHz, during 100 Mb/s operation RX_CLK is 25 MHz and during 10 Mb/s this is
2.5 MHz.
Receive PMA Clock 1: In TBI mode, this 62.5Mhz clock is used in conjunction
with RXPMACLK0 to clock 10-bit TBI data into the DP83821. The rising edge of
RXPMACLK1 clocks the even-numbered bytes.
I Gigabit Receive Data: This is a group of 8 signals, sourced from an external
PMD, that contains data aligned on byte boundaries and are driven
synchronous to the RX_CLK. RXD7 is most significant bit.
Receive Data: This is a group of 4 signals, sourced from an external PMD, that
contains data aligned on nibble boundaries and are driven synchronous to the
RX_CLK. RXD3 is the most significant bit and RXD0 is the least significant bit.
RXD7 through RXD4 are not used in this mode.
TBI Receive Data: In TBI mode, these bits are the lower 8 bits of the 10-bit TBI
Receive data.
I Receive Data Valid: This indicates that the external PMD is presenting
recovered and decoded nibbles on the RXD signals, and that RX_CLK is
synchronous to the recovered data in 100 Mb/s operation. This signal will
encompass the frame, starting with the Start-of-Frame delimiter (JK) and
excluding any End-of-Frame delimiter (TR).
TBI Receive Data: In TBI mode, this is RXD8 of the 10-bit TBI Receive data.
I Receive Error: This signal is asserted high synchronously by the external PMD
whenever it detects a media error and RXDV is asserted in 100 Mb/s or 1000
Mb/s operation.
TBI Receive Data: In TBI mode, this is RXD9 of the 10-bit TBI Receive data.
O Receive Output Enable: This pin is used to disable an external PMD while the
BIOS ROM is being accessed.
I MII Transmit Clock: A continuous clock that is sourced by the external PMD.
During 100 Mb/s operation this is 25 MHz +/- 100 ppm. During 10 Mb/s
operation this clock is 2.5 MHz +/- 100 ppm.
Receive PMA Clock 0: In TBI mode, this 62.5Mhz clock is used in conjunction
with RXPMACLK1 to clock 10-bit TBI data into the DP83821. The rising edge of
RXPMACLK0 clocks the odd-numbered bytes.
O Gigabit Transmit Data: This is a group of 8 signals which are driven
synchronous to GTXCLK. TXD7 is the most significant bit.
Transmit Data: This is a group of 4 data signals which are driven synchronous
to the TXCLK for transmission to the external PMD. TXD3 is the most
significant bit and TXD0 is the least significant bit. TXD7 through TXD4 are not
used in this mode
TBI Transmit Data: In TBI mode, this is the lower 8 bits of the 10-bit TBI
Transmit data.
BIOS ROM Address: During external BIOS ROM access, these signals
become part of the ROM address.
O Transmit Enable: This signal is synchronous to TXCLK and provides precise
framing for data carried on TXD3-0 for the external PMD. It is asserted when
TXD3-0 contains valid data to be transmitted.
TBI Transmit Data: In TBI mode, this is TXD8 of the 10-bit TBI Transmit data.
5 www.national.com

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DP83821 arduino
3.0 Functional Description (Continued)
3.2 PCI Bus Interface
3.2.1 Byte Ordering
The DP83821 implements the Peripheral Component
Interconnect (PCI) bus interface as defined in PCI Local
Bus Specification Version 2.2. When internal register are
being accessed the DP83821 acts as a PCI target (slave).
When accessing host memory for descriptor or packet data
transfer, the DP83821 acts as a PCI bus master.
All required pins and functions are implemented. The
optional interface pin INTA for support of interrupt requests
is implemented as well. The bus interface supports 32-bit
and 33Mhz operation.
For more information, refer to the PCI Local Bus
Specification version 2.2, December 18, 1998.
The DP83821 can be configured to order the bytes of data
on the AD[31:0] bus to conform to Little Endian or Big
Endian ordering through the use of the CFG:BEM bit. Byte
ordering only affects bus mastered packet data transfers in
32-bit mode. Register information remains bit aligned (i.e.
AD[31] maps to bit 31 in any register space, AD[0] maps to
bit 0, etc.) when registers are accessed with 32-bit
operations. Bus mastered transfers of buffer descriptor
information also remain bit aligned.
When configured for Little Endian (CFG:BEM=0), the byte
orientation for receive and transmit data and descriptors in
system memory is as follows:
Figure 3-2 Little Endian Byte Ordering
31
24 23
16 15
87
0
Byte 3
Byte 2
Byte 1
Byte 0
C/BEN[3]
(MSB)
C/BEN[2]
C/BEN[1]
C/BEN[0]
(LSB)
When configured for big-endian mode (CFG:BEM=1), the
byte orientation for receive and transmit data and
descriptors in system memory is as follows:
Figure 3-3 Big Endian Byte Ordering
31
24 23
16 15
87
0
Byte 0
Byte 1
Byte 2
Byte 3
C/BEN[3]
(LSB)
C/BEN[2]
C/BEN[1]
C/BEN[0]
(MSB)
3.2.2 Interrupt Control
Interrupts are performed by asynchronously asserting the
INTAN pin. This pin is an open drain output. The source of
the interrupt can be determined by reading the Interrupt
Status Register (ISR) (See Section 4.2.6). One or more
bits in the ISR will be set, denoting all currently pending
interrupts. Reading of the ISR clears ALL bits. Masking of
specific interrupts can be accomplished by using the
Interrupt Mask Register (IMR) (See Section 4.2.7).
Assertion of INTAN can be prevented by clearing the
Interrupt Enable bit in the Interrupt Enable Register (See
Section 4.2.8). This allows the system to defer interrupt
processing as needed.
3.2.3 Latency Timer
The Latency Timer described in CFGLAT:LAT (See Section
4.1.4) defines the maximum number of bus clocks that the
device will hold the bus. Once the device gains control of
the bus and issues FRAMEN, the Latency Timer will begin
counting down. If GNTN is deasserted before the DP83821
has finished with the bus, the device will maintain
ownership of the bus until the timer reaches zero (or has
finished the bus transfer). The timer is an 8-bit counter, with
the lower 4 bits hard-coded to 1111b. This means that the
timer value can only be incremented in units of 16 clocks.
3.2.4 32-Bit Data Operation
The DP83821 supports only 32-bit operation as a bus
master or target for transferring descriptor and packet data
information. At the rising edge of RSTN, the DP83821
samples the REQ64N pin and determines the bus to be 32-
bit capable. Since this pin must be tied high, it indicates the
bus is not 64-bit capable
3.2.5 32-Bit Addressing
The DP83821 supports only 32-bit addressing as a bus
master or target for transferring descriptor and packet data
information. This mode must be enabled through
configuration from EEPROM.
3.3 Bus Operation
3.3.1 Target Read
A Target Read operation starts with the system generating
FRAMEN, Address, and either an IO read (0010b) or
Memory Read (0110b) command. See Figure 3-4. If the
32-bit address on the address bus matches the IO address
range specified in CFGIOA:IOBASE (for I/O reads) or the
memory address range specified in CFGMA:MEMBASE
(for memory reads), the DP83821 will generate DEVSELN
2 clock cycles later (medium speed).
The system must tri-state the Address bus, and convert the
C/BEN bus to byte enables, after the address cycle. On the
2nd cycle after the assertion of DEVSELN, all 32-bits of
data and TRDYN will become valid. If IRDYN is asserted at
that time, TRDYN will be forced HIGH on the next clock for
1 cycle, and then tri-stated.
If FRAMEN is asserted beyond the assertion of IRDYN, the
DP83821 will still make data available as described above,
but will also issue a Disconnect. That is, it will assert the
STOPN signal with TRDYN. STOPN will remain asserted
until FRAMEN is detected as deasserted.
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