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PDF W78ERD2A Data sheet ( Hoja de datos )

Número de pieza W78ERD2A
Descripción 8-BIT MICROCONTROLLER
Fabricantes Winbond 
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No Preview Available ! W78ERD2A Hoja de datos, Descripción, Manual

W78ERD2/W78ERD2A Data Sheet
www.DataSheet4U.com
Table of Contents-
8-BIT MICROCONTROLLER
1. GENERAL DESCRIPTION ......................................................................................................... 3
2. FEATURES ................................................................................................................................. 3
3. PIN CONFIGURATIONS ............................................................................................................ 4
4. PIN DESCRIPTION..................................................................................................................... 5
5. FUNCTIONAL DESCRIPTION ................................................................................................... 6
5.1 RAM ................................................................................................................................ 6
5.2 Timers/Counters ............................................................................................................. 6
5.3 Clock ............................................................................................................................... 7
5.4 Power Management........................................................................................................ 7
5.5 Reduce EMI Emission .................................................................................................... 7
5.6 Reset............................................................................................................................... 7
6. SPECIAL FUNCTION REGISTER.............................................................................................. 8
7. PORT 4 AND BASE ADDRESS REGISTERS ......................................................................... 30
8. INTERRUPTS ........................................................................................................................... 32
8.1 External Interrupts 2 and 3 ........................................................................................... 32
8.2 Interrupt Priority ............................................................................................................ 32
9. PROGRAMMABLE TIMERS/COUNTERS ............................................................................... 33
9.1 Timer 0 and Timer 1 ..................................................................................................... 33
9.2 Timer/Counter 2............................................................................................................ 35
10. ENHANCED FULL DUPLEX SERIAL PORT............................................................................ 38
10.1 MODE 0 ........................................................................................................................ 38
10.2 MODE 1 ........................................................................................................................ 39
10.3 MODE 2 ........................................................................................................................ 40
10.4 MODE 3 ........................................................................................................................ 41
10.5 Framing Error Detection ............................................................................................... 42
10.6 Multi-Processor Communications................................................................................. 42
11. PROGRAMMABLE COUNTER ARRAY (PCA) ........................................................................ 44
11.1 PCA Capture Mode....................................................................................................... 47
11.2 16-bit Software Timer Comparator Mode ..................................................................... 47
11.3 High Speed Output Mode ............................................................................................. 48
11.4 Pulse Width Modulator Mode ....................................................................................... 49
11.5 Watchdog Timer ........................................................................................................... 49
12. HARDWARE WATCHDOG TIMER (ONE-TIME ENABLED WITH RESET-OUT) ................... 50
Publication Release Date: February 14, 2007
- 1 - Revision A10

1 page




W78ERD2A pdf
W78ERD2/W78ERD2A
4. PIN DESCRIPTION
SYMBOL
EA
TYPE*
DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute
I instructions in external ROM. The ROM address and data are not presented
on the bus if the EA pin is high.
PSEN
ALE
RST
XTAL1
XTAL2
VSS
VDD
P0.0 P0.7
P1.0 P1.7
P2.0 P2.7
P3.0 P3.7
P4.0 P4.3
PROGRAM STORE ENABLE: PSEN indicates external ROM data is on the
O H Port 0 address/data bus. If internal ROM is accessed, no PSEN strobe signal
is present on this pin.
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
O H separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency.
IL
RESET: If this pin is set high for two machine cycles while the oscillator is
running, the W78ERD2 is reset.
I CRYSTAL 1: Crystal oscillator input or external clock input.
O CRYSTAL 2: Crystal oscillator output.
I GROUND: ground potential.
I POWER SUPPLY: Supply voltage for operation.
PORT 0: 8-bit, bi-directional I/O port, the same as that of the standard 80C52.
I/O D Port 0 has internal pull-up resisters enabled by software.
I/O H PORT 1: 8-bit, bi-directional I/O port, the same as that of the standard 80C52.
I/O H
PORT 2: 8-bit, bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits when accessing external memory.
I/O H PORT 3: 8-bit, bi-directional I/O port, the same as that of the standard 80C52.
I/O H PORT 4: 4-bit, bi-directional I/O port with chip-select functions.
* Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
Publication Release Date: February 14, 2007
- 5 - Revision A10

5 Page





W78ERD2A arduino
W78ERD2/W78ERD2A
BIT NAME
FUNCTION
Timer 1 overflow flag: This bit is set when Timer 1 overflows. It is cleared
7 TF1 automatically when the program does a timer 1 interrupt service routine. It can also
be set or cleared by software.
6
TR1
1: Turn on Timer 1.
0: Turn off Timer 1.
Timer 0 overflow flag: This bit is set when Timer 0 overflows. It is cleared
5 TF0 automatically when the program does a timer 0 interrupt service routine. It can also
be set or cleared by software.
4
TR0
1: Turn on Timer 0.
0: Turn off Timer 0.
Interrupt 1 Edge Detect: This bit is set by the hardware when a falling-edge / low-
3 IE1 level is detected on INT1 . If INT1 is edge-triggered, this bit is cleared by the
hardware when the interrupt service routine begins. Otherwise, it follows the pin.
Interrupt 1 type control
2 IT1 1: Interrupt 1 is triggered by a falling-edge on INT1 .
0: Interrupt 1 is triggered by a low-level on INT1 .
Interrupt 0 Edge Detect: This bit is set by the hardware when a falling-edge / low-
1 IE0 level is detected on INT0 . If INT0 is edge-triggered, this bit is cleared by the
hardware when the interrupt service routine begins. Otherwise, it follows the pin.
Interrupt 0 type control
0 IT0 1: Interrupt 0 is triggered by a falling-edge on INT0 .
0: Interrupt 0 is triggered by a low-level on INT0 .
Timer Mode Control
Bit: 7 6 5 4 3 2 1 0
GATE C/T M1 M0 GATE C/T M1 M0
Mnemonic: TMOD
Address: 89h
BIT NAME
FUNCTION
Gating control: When this bit is set, Timer/Counter 1 is enabled only while the INT1
7 GATE pin is high and the TR1 control bit is set. When cleared, the INT1 pin has no effect,
and Timer 1 is enabled whenever TR1 is set.
6
C/ T
Timer or Counter Select: When cleared, Timer 1 is incremented by the internal
clock. When set, Timer 1 counts falling edges on the T1 pin.
5 M1 Timer 1 Mode Select bits: See below.
4 M0 Timer 1 Mode Select bits: See below.
- 11 -
Publication Release Date: February 14, 2007
Revision A10

11 Page







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