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PDF M36L0R7060B1 Data sheet ( Hoja de datos )

Número de pieza M36L0R7060B1
Descripción (M36L0R7060T1 / M36L0R7060B1) Flash memory
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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No Preview Available ! M36L0R7060B1 Hoja de datos, Descripción, Manual

M36L0R7060T1
M36L0R7060B1
128 Mbit (Multiple Bank, Multilevel, Burst) Flash memory
and 64 Mbit (Burst) PSRAM, 1.8 V supply, multichip package
Features
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Multichip package
– 1 die of 128 Mbit (8 Mb x16, Multiple Bank,
Multilevel, Burst) Flash memory
– 1 die of 64 Mbit (4 Mb x16) Pseudo SRAM
Supply voltage
– VDDF = VCCP = VDDQF = 1.7 to 1.95 V
– VPPF = 9 V for fast program
Electronic signature
– Manufacturer Code: 20h
– Top Device Code
M36L0R7060T1: 88C4h
– Bottom Device Code
M36L0R7060B1: 88C5h
Package
– ECOPACK®
Flash memory
Synchronous / Asynchronous Read
– Synchronous Burst Read mode: 54 MHz,
66 MHz
– Random Access: 70 ns, 85 ns
Synchronous Burst Read Suspend
Programming time
– 2.5 µs typical word program time using
Buffer Enhanced Factory Program
command
Memory organization
– Multiple Bank memory array: 8 Mbit banks
– Parameter Blocks (top or bottom location)
Common Flash Interface (CFI)
100 000 program/erase cycles per block
Dual operations
– program/erase in one Bank while read in
others
– No delay between read and write
operations
FBGA
TFBGA88 (ZAQ)
8 x 10 mm
Security
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
Block locking
– All blocks locked at power-up
– Any combination of blocks can be locked
with zero latency
– WPF for Block Lock-Down
– Absolute Write Protection with VPPF = VSS
PSRAM
Access time: 70 ns
Asynchronous Page Read
– Page Size: 4, 8 or 16 words
– Subsequent read within page: 20 ns
Low power features
– Automatic Temperature-compensated Self-
Refresh (TCR)
– Partial Array Self-Refresh (PASR)
– Deep Power-Down (DPD) mode
Synchronous Burst Read/Write
May 2007
Rev 1
1/22
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1

1 page




M36L0R7060B1 pdf
M36L0R7060T1, M36L0R7060B1
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
TFBGA88 8 × 10 mm, 8 × 10 ball array - 0.8 mm pitch, package outline . . . . . . . . . . . . . . 18
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M36L0R7060B1 arduino
M36L0R7060T1, M36L0R7060B1
Signal descriptions
2.11
PSRAM Chip Enable input (EP)
The Chip Enable input activates the PSRAM when driven Low (asserted). When de-
asserted (VIH), the device is disabled, and goes automatically in low-power Standby mode
or Deep Power-down mode, according to the RCR settings.
2.12
PSRAM Write Enable (WP)
Write Enable, WP, controls the Bus Write operation of the PSRAM. When asserted (VIL), the
device is in Write mode and Write operations can be performed either to the configuration
registers or to the memory array.
2.13
PSRAM Output Enable (GP)
When held Low, VIL, the Output Enable, GP, enables the Bus Read operations of the
memory.
2.14
PSRAM Upper Byte Enable (UBP)
The Upper Byte En-able, UBP, gates the data on the Upper Byte Data inputs/outputs (DQ8-
DQ15) to or from the upper part of the selected address during a Write or Read operation.
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2.15
2.16
PSRAM Lower Byte Enable (LBP)
The Lower Byte Enable, LBP, gates the data on the Lower Byte Data inputs/outputs (DQ0-
DQ7) to or from the lower part of the selected address during a Write or Read operation.
If both LBP and UBP are disabled (High) during an operation, the device will disable the data
bus from receiving or transmitting data. Although the device will seem to be deselected, it
remains in an active mode as long as EP remains Low.
PSRAM Configuration Register Enable (CRP)
When this signal is driven High, VIH, bus read or write operations access either the value of
the Refresh Configuration Register (RCR) or the Bus Configuration Register (BCR)
according to the value of A19.
2.17
VDDF supply voltage
VDDF provides the power supply to the internal core of the Flash memory. It is the main
power supply for all Flash memory operations (Read, Program and Erase).
2.18
VCCP supply voltage
VCCP provides the power supply to the internal core of the PSRAM device. It is the main
power supply for all PSRAM operations.
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