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PDF M58WR064T Data sheet ( Hoja de datos )

Número de pieza M58WR064T
Descripción (M58WR064B/T) FLASH MEMORY
Fabricantes STMicroelectronics 
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M58WR064T
M58WR064B
64 Mbit (4Mb x 16, Multiple Bank, Burst )
1.8V Supply Flash Memory
PRODUCT PREVIEW
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FEATURES SUMMARY
s SUPPLY VOLTAGE
– VDD = 1.65V to 2.2V for Program, Erase and
Read
– VDDQ = 1.65V to 3.3V for I/O Buffers
– VPP = 12V for fast Program (optional)
s SYNCHRONOUS / ASYNCHRONOUS READ
– Synchronous Burst Read mode : 52MHz
– Asynchronous/ Synchronous Page Read
mode
– Random Access: 70, 85, 100 ns
s PROGRAMMING TIME
– 8µs by Word typical for Fast Factory Program
– Double/Quadruple Word Program option
– Enhanced Factory Program options
s MEMORY BLOCKS
– Multiple Bank Memory Array: 4 Mbit Banks
– Parameter Blocks (Top or Bottom location)
s DUAL OPERATIONS
– Program Erase in one Bank while Read in
others
– No delay between Read and Write operations
s BLOCK LOCKING
– All blocks locked at Power up
– Any combination of blocks can be locked
– WP for Block Lock-Down
s SECURITY
– 128 bit user programmable OTP cells
– 64 bit unique device number
– One parameter block permanently lockable
s COMMON FLASH INTERFACE (CFI)
s 100,000 PROGRAM/ERASE CYCLES per
BLOCK
Figure 1. Packages
FBGA
VFBGA56 (ZB)
7.7 x 9 mm
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code, M58WR064T: 8810h
– Bottom Device Code, M58WR064B: 8811h
April 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
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M58WR064T pdf
M58WR064T, M58WR064B
Table 24. Reset and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 17. VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Bottom View Package Outline. . . 51
Table 25. VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Package Mechanical Data . . . . . . 51
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 26. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 27. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
APPENDIX A. BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 28. Top Boot Block Addresses, M58WR064T. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 29. Bottom Boot Block Addresses, M58WR064B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
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APPENDIX B. COMMON FLASH INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 30. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 31. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 32. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 33. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 34. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 35. Protection Register Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 36. Burst Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 37. Bank and Erase Block Region Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 38. Bank and Erase Block Region 1 Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 39. Bank and Erase Block Region 2 Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
APPENDIX C. FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 18. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 19. Double Word Program Flowchart and Pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 20. Quadruple Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 21. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 68
Figure 22. Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 23. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 24. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 25. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 72
Figure 26. Enhanced Factory Program Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Enhanced Factory Program Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 27. Quadruple Enhanced Factory Program Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Quadruple Enhanced Factory Program Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
APPENDIX D. COMMAND INTERFACE STATE TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 40. Command Interface States - Modify Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 41. Command Interface States - Modify Table, Next Output. . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 42. Command Interface States - Lock Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 43. Command Interface States - Lock Table, Next Output . . . . . . . . . . . . . . . . . . . . . . . . . . 80
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M58WR064T arduino
M58WR064T, M58WR064B
age). See Figure 9, AC Measurement Load Cir-
cuit. The PCB trace widths should be sufficient
to carry the required VPP program and erase
currents.
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BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Ad-
dress Latch, Output Disable, Standby and Reset.
See Table 3, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect Bus Write operations.
Bus Read. Bus Read operations are used to out-
put the contents of the Memory Array, the Elec-
tronic Signature, the Status Register and the
Common Flash Interface. Both Chip Enable and
Output Enable must be at VIL in order to perform a
read operation. The Chip Enable input should be
used to enable the device. Output Enable should
be used to gate data onto the output. The data
read depends on the previous command written to
the memory (see Command Interface section).
See Figures 10 and 11, Asynchronous Read AC
Waveforms, and Table 20, Asynchronous Read
AC Characteristics, for details of when the output
becomes valid.
Bus Write. Bus Write operations write Com-
mands to the memory or latch Input Data to be
programmed. A bus write operation is initiated
when Chip Enable and Write Enable are at VIL with
Output Enable at VIH. Commands, Input Data and
Addresses are latched on the rising edge of Write
Enable or Chip Enable, whichever occurs first. The
addresses can also be latched prior to the write
operation by toggling Latch Enable. In this case
the Latch Enable should be tied to VIH during the
bus write operation.
See Figures 14 and 15, Write AC Waveforms, and
Tables 22 and 23, Write AC Characteristics, for
details of the timing requirements.
Address Latch. Address latch operations input
valid addresses. Both Chip enable and Latch En-
able must be at VIL during address latch opera-
tions. The addresses are latched on the rising
edge of Latch Enable.
Output Disable. The outputs are high imped-
ance when the Output Enable is at VIH.
Standby. Standby disables most of the internal
circuitry allowing a substantial reduction of the cur-
rent consumption. The memory is in stand-by
when Chip Enable and Reset are at VIH. The pow-
er consumption is reduced to the stand-by level
and the outputs are set to high impedance, inde-
pendently from the Output Enable or Write Enable
inputs. If Chip Enable switches to VIH during a pro-
gram or erase operation, the device enters Stand-
by mode when finished.
Reset. During Reset mode the memory is dese-
lected and the outputs are high impedance. The
memory is in Reset mode when Reset is at VIL.
The power consumption is reduced to the Standby
level, independently from the Chip Enable, Output
Enable or Write Enable inputs. If Reset is pulled to
VSS during a Program or Erase, this operation is
aborted and the memory content is no longer valid.
Table 3. Bus Operations
Operation
E GW L
Bus Read
Bus Write
VIL VIL VIH VIL(2)
VIL VIH VIL VIL(2)
Address Latch
VIL X VIH VIL
Output Disable
Standby
Reset
VIL VIH VIH
VIH X
X
XXX
X
X
X
Note: 1. X = Don’t care.
2. L can be tied to VIH if the valid address has been previously latched.
3. Depends on G.
RP WAIT(4)
DQ15-DQ0
VIH Data Output
VIH Data Input
VIH Data Output or Hi-Z (3)
VIH Hi-Z
VIH Hi-Z
Hi-Z
VIL Hi-Z
Hi-Z
11/81

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