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PDF DL5064 Data sheet ( Hoja de datos )

Número de pieza DL5064
Descripción (DL5500 Series) The Industry's First Fast Field Programmable Gate Array
Fabricantes DynaChip 
Logotipo DynaChip Logotipo



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Features
• Fast Field Programmable Gate Arrays
• Patented Active RepeaterArchitecture
• Data and Clock Rates up to 270 MHz
• Complex operations up to 200 MHz
• Input Block Register Setup Time 800 ps
• Output Block Register Clock-to-out 1.6 ns
• ECL, PECL and GTL Interface Levels
• 100K and 100KH Compatible
• Differential Outputs
• 1,000 to 10,000 Gates
• 6 Low-skew Clock Trees
• Highly Predictable, Fanout Independent
Routing Delays
• SRAM-based Programming
• JTAG Boundary Scan
• Fully Automatic Implementation Using
DynaTool
Applications Examples
Telecommunications and
Datacommunications
Sonet and ATM Interfaces
Satellite Communications
FDDI
• Test and Instrumentation
VLSI and Memory Testers
Oscilloscopes and Logic Analyzers
• High-Speed Graphics
Real-Time Video Imaging
HDTV
• Servers and Peripherals
High-speed Servers
High-speed Bus Interfaces
Fast Graphics Interfaces
• Emulation
DL5000Family
Fast Field Programmable Gate Array
9P6D4G1L2502856
Introduction
The DL5000 is the industry’s first Fast Field Pro-
grammable Gate Array (FFPGA) family. Utilizing
a breakthrough in field programmable interconnect
techniques called Active Repeaters, this family pro-
vides unprecedented system level performance.
High operating frequencies combined with fast
ECL, GTL and PECL input and output structures
make these devices ideal for high-speed interfac-
es, subsystems and core logic.
DL5000 family devices are ideal for applications
where other FPGAs can not meet performance re-
quirements. They are also ideal for applications
where designers want to integrate many discrete
ECL devices.
Benefits to the user include ultra high-speed, fast
time-to-market, reduced risk and maximum de-
sign flexibility.
The DL5000 features SRAM-based programming
allowing the devices to be configured in-circuit
and reprogrammed on-the-fly. They can be re-
configured an unlimited number of times provid-
ing maximum flexibility for design iterations and
field upgrades.
Device
DL5064
DL5256
DL5528
Gates
1,250
5,000
10,000
Logic
Blocks
64
256
528
Input
Blocks
48
76
104
Output
Blocks
49
76
112
Flip Flops
212
664
1,272
Clock
Trees
6
6
6
Datasheet
November 1998

1 page




DL5064 pdf
www.DataSheet4U.com
DL5000 - Fast Field Programmable Gate Array
long distance or drive a large number of loads.
In contrast, DynaChip uses Active Repeaters to create programmable interconnec-
tions. These repeaters buffer the signal at every interconnection point and isolate the
capacitance of the rest of the net.
The result is fast, predictable performance even for long, high fanout nets.
Conventional Passive Interconnect
Logic
Block
R
C
R
C
R
R
C
DynaChip's Active Interconnect
Logic
Block
CC
C
Figure 1: Active vs. Passive Interconnect
In FPGA devices that use pass-gate based interconnect, net delays increase quadrat-
ically with the number of programmable interconnect points, as shown in figure 2.
DynaChip devices use Active Repeater interconnect making net delays linear. The
result is much higher performance and greater predictability.
DynaChip
# of Connections
Passive Interconnect
Active Repeater
Figure 2: Active Repeatervs. Passive Interconnect
November 1998
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DL5064 arduino
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DL5000 - Fast Field Programmable Gate Array
Output Block
R
QD
PC
From Global Set/Reset Line
From Routing Channels
CLK
PC
From Global Clock Array 1
From Global Clock Array 2
From Right or Left Output Clock Array
Scan-Out
D QD Q
Mode
Output
Pad
Shift
DR
CLK
CLK
Scan-In
Clock
DR
Update
DR
Figure 8: Output Block Diagram
Figure 8 shows the resources in the DL5000 output block. Each output block contains
a direct path out of the device and a path that includes an edge triggered flip flop.
Additional flip flops and muxes support JTAG Boundary Scan
All outputs must be terminated through a 50resistor to a supply 2V below the top
supply. For example, if supply voltages of 0V and -4.5V are used, termination is to -2V.
Differential Outputs
To create differential outputs, connect the output signal to two output pins and in-
vert one of the outputs as shown in figure 9. During implementation, use placement
constraints or the DynaTool Design Editor to insure that the pins are placed next to
each other.
Differential outputs should only be used when the output signal is registered using
the flip flop in the output block. This insures that there is no skew between the dif-
ferential pairs.
DynaChip
November 1998
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