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PDF FW82815 Data sheet ( Hoja de datos )

Número de pieza FW82815
Descripción Graphics and Memory Controller Hub
Fabricantes Intel 
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No Preview Available ! FW82815 Hoja de datos, Descripción, Manual

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Intel815 Chipset Family: 82815
Graphics and Memory Controller
Hub (GMCH)
Datasheet
June 2000
Document Reference Number: 290688-001

1 page




FW82815 pdf
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82815 GMCH
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3.5.8. MLT1—Master Latency Timer Register (Device 1) .....................................89
3.5.9. HDR1—Header Type Register (Device 1) ...................................................89
3.5.10. PBUSN—Primary Bus Number Register (Device 1)....................................89
3.5.11. SBUSN—Secondary Bus Number Register (Device 1) ...............................90
3.5.12. SUBUSN—Subordinate Bus Number Register (Device 1) ..........................90
3.5.13. SMLT—Secondary Master Latency Timer Register (Device 1) ...................91
3.5.14. IOBASE—I/O Base Address Register (Device 1) ........................................92
3.5.15. IOLIMIT—I/O Limit Address Register (Device 1).........................................93
3.5.16. SSTS—Secondary PCI-PCI Status Register (Device 1)..............................94
3.5.17. MBASE—Memory Base Address Register (Device 1).................................95
3.5.18. MLIMIT—Memory Limit Address Register (Device 1) .................................96
3.5.19. PMBASE—Prefetchable Memory Base Address Register (Device 1) .........97
3.5.20. PMLIMIT—Prefetchable Memory Limit Address Register (Device 1)..........98
3.5.21. BCTRL—PCI-PCI Bridge Control Register (Device 1).................................99
3.5.22. ERRCMD1—Error Command Register (Device 1) ....................................101
3.6. Graphics Device Registers (Device 2: VISIBLE IN GFX Mode Only) .........................102
3.6.1. VID2—Vendor Identification Register (Device 2).......................................103
3.6.2. DID2—Device Identification Register (Device 2) .......................................103
3.6.3. PCICMD2—PCI Command Register (Device 2)........................................104
3.6.4. PCISTS2—PCI Status Register (Device 2) ...............................................105
3.6.5. RID2—Revision Identification Register (Device 2) ....................................106
3.6.6. PI—Programming Interface Register (Device 2) .......................................106
3.6.7. SUBC2—Sub-Class Code Register (Device 2) .........................................106
3.6.8. BCC2—Base Class Code Register (Device 2) ..........................................107
3.6.9. CLS—Cache Line Size Register (Device 2) ..............................................107
3.6.10. MLT2—Master Latency Timer Register (Device 2) ...................................107
3.6.11. HDR2—Header Type Register (Device 2) .................................................108
3.6.12. BIST—BIST Register (Device 2)................................................................108
3.6.13. GMADR—Graphics Memory Range Address Register (Device 2)...........109
3.6.14. MMADR—Memory Mapped Range Address Register (Device 2) .............110
3.6.15. SVID—Subsystem Vendor Identification Register (Device 2)....................110
3.6.16. SID—Subsystem Identification Register (Device 2)...................................111
3.6.17. ROMADR—Video BIOS ROM Base Address Register (Device 2) ............111
3.6.18. CAPPOINT—Capabilities Pointer Register (Device 2) ..............................111
3.6.19. INTRLINE—Interrupt Line Register (Device 2) ..........................................112
3.6.20. INTRPIN—Interrupt Pin Register (Device 2)..............................................112
3.6.21. MINGNT—Minimum Grant Register (Device 2).........................................112
3.6.22. MAXLAT—Maximum Latency Register (Device 2)....................................112
3.6.23. PM_CAPID—Power Management Capabilities ID Register (Device 2).....113
3.6.24. PM_CAP—Power Management Capabilities Register (Device 2) .............113
3.6.25. PM_CS—Power Management Control/Status Register (Device 2) ..........114
3.7. Display Cache Interface ...............................................................................................115
3.7.1. DRT—DRAM Row Type ............................................................................115
3.7.2. DRAMCL—DRAM Control Low .................................................................116
3.7.3. DRAMCH—DRAM Control High ................................................................117
3.8. Display Cache Detect and Diagnostic Registers..........................................................118
3.8.1. GRX—GRX Graphics Controller Index Register .......................................118
3.8.2. MSRMiscellaneous Output.....................................................................119
3.8.3. GR06Miscellaneous Register.................................................................119
3.8.4. GR10Address Mapping ..........................................................................120
3.8.5. GR11Page Selector ...............................................................................120
Datasheet
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FW82815 arduino
82815 GMCH
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82815 GMCH Features
! Processor/Host Bus Support
IntelPentiumIII processor and Intel® Celeron™
! Integrated Graphics Controller Multiplexed with AGP
Controller
Processor in FC-PGA package
3D Hyper Pipelined Architecture
Supports processor 370-Pin Socket
-Parallel Data Processing (PDP)
Supports 32-Bit System Bus Addressing
-Precise Pixel Interpolation (PPI)
4 deep in-order queue; 4 or 1 deep request queue
Full 2D H/W Acceleration
Supports Uni-processor systems only
Motion Video Acceleration
In-order and Dynamic Deferred Transaction Support
Supports 133 MHz System Memory while running in
66/100/133MHz System Bus Frequency
non-CPC mode
GTL+ I/O Buffer
! Integrated SDRAM Controller
! 3D Graphics Visual Enhancements
Flat & Gouraud Shading
32 MB to 512 MB using 16Mb/64Mb/128Mb/256Mb
Mip Maps with Trilinear and Anisotropic Filtering
technology
Full Color Specular
Supports up to 3 double sided DIMMs at 100 MHz system Fogging Atmospheric Effects
memory bus
Z Buffering
Supports up to 2 double sided or 3 single sided DIMMs at 3D Pipe 2D Clipping
133 MHz system memory bus.
Backface Culling
64-bit data interface
100/133 MHz system memory bus frequency
Support for Asymmetrical SDRAM addressing only
Support for x8 and x16 SDRAM device width
Unbuffered, Non-ECC SDRAM only supported
Refresh Mechanism: CBR ONLY supported
Enhanced Open page arbitration SDRAM paging scheme
Suspend to RAM support
! Accelerated Graphics Port (AGP) Interface Multiplexed with
Internal Graphics
Supports a single AGP device via a connector
Supports AGP 2.0 including 4x AGP data transfers
AGP Universal Connector support via dual mode buffers
! 3D Graphics Texturing Enhancements
Per Pixel Perspective Correction Texture Mapping
Texture Compositing
Texture Color Keying/Chroma Keying
! Digital Video Output
85 MHz Flat Panel Monitor/Digital CRT Interface Or
Digital Video Output for use with a external TV encoder
! Display
Integrated 24-bit 230 MHz RAMDAC
Gamma Corrected Video
DDC2B Compliant
! 2D Graphics
to allow AGP 2.0 3.3V or 1.5V signaling
Up to 1600x1200 in 8-bit Color at 85 Hz Refresh
AGP PIPE# or SBA initiated accesses to SDRAM not
Hardware Accelerated Functions
snooped
3 Operand Raster BitBLTs
AGP FRAME# initiated accesses to SDRAM are snooped
64x64x3 Color Transparent Cursor
High priority access support
Hierarchical PCI configuration mechanism
Delayed transaction support for AGP-to-SDRAM reads
that can not be serviced immediately
! Arbitration Scheme and Concurrency
! Arithmetic Stretch Blitter Video
H/W Motion Compensation Assistance for S/W MPEG2
Decode
Software DVD at 30 fps
Digital Video Out Port
Intelligent Centralized Arbitration Model for Optimum
NTSC and PAL TV Out Support
Concurrency Support
H/W Overlay Engine with Bilinear Filtering
Concurrent operations of processor and System busses
Independent gamma correction, saturation, brightness &
supported via dedicated arbitration and data buffering
! Data Buffering
Distributed Data Buffering Model for optimum
contrast for overlay
! Integrated Graphics Memory Controller
IntelD.V.M. Technology
concurrency
SDRAM Write Buffer with read-around-write capability
Dedicated processor –SDRAM, hub interface-SDRAM
and Graphics-SDRAM Read Buffers
! Power Management Functions
SMRAM space remapping to A0000h (128 KB)
Optional Extended SMRAM space above 256 MB,
additional 512 KB / 1MB TSEG from Top of Memory,
cacheable
Stop Clock Grant and Halt special cycle translation from
the host to the hub interface
ACPI Compliant power management
! Display Cache Interface multiplexed on the AGP interface
32-bit data interface
133 MHz SDRAM interface only.
Flexible AGP In-Line Memory Module (AIMM)
Implementation
Support for 2 1Mx16, or 1 2Mx32 on AIMM card
4 MB maximum addressable
! Supporting I/O Bridge
82801AA I/O Controller Hub (ICH)
82801BA I/O Controller Hub (ICH2)
! Packaging/Power
APIC Buffer Management
544 BGA
SMI, SCI, and SERR error indication
1.85V core with 3.3V CMOS I/O
Datasheet
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