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PDF IR3084U Data sheet ( Hoja de datos )
| Número de pieza | IR3084U | |
| Descripción | OPTERON/ATHLON64 CONTROL IC | |
| Fabricantes | International Rectifier | |
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IR3084U
Data Sheet No. PD94719
XPHASETM VR10, VR11 & OPTERON/ATHLON64 CONTROL IC
DESCRIPTION
The IR3084U Control IC combined with an IR XPhaseTM Phase IC provides a full featured and flexible
way to implement a complete VR10, VR11, Opteron, or Athlon64 power solution. The “Control” IC
provides overall system control and interfaces with any number of “Phase” ICs which each drive and
monitor a single phase of a multiphase converter. The XPhaseTM architecture results in a power supply
that is smaller, less expensive, and easier to design while providing higher efficiency than conventional
approaches.
The IR3084U is based on the IR3084 VR10 Control IC, but incorporates the following modifications;
• Supports VR11 7-bit VID, VR10 7-bit extended VID, and Opteron/Athlon64 5-bit VID codes
• Supports both VR11 and legacy Opteron/Athlon64 start-up sequences
• VID Select pin sets the DAC to VR10, VR11, or Opteron/Athlon64
• INTL_MD output pin indicates which DAC is selected – Intel or AMD
• VOSENS− float detection protects the CPU in the event that the VOSENS− trace is broken
• Enable Input Thresholds set by VID Select pin to either VR10, VR11 or Opteron/Athlon64
• VID Input Thresholds set by VID Select pin to either 0.6V (VR10/VR11) or 1.24V (AMD)
• No-Load Setpoint Current changes polarity based on VID Select to accommodate VR10, VR11
(negative offset from DAC) or Opteron/Athlon64 (positive offset from DAC).
FEATURES
www.DataSheet4U.com
• 1 to X phase operation with matching Phase IC
• 7-bit VR 10/11 compatible VID with 0.5% overall system set point accuracy
• 5-bit Opteron/Athlon64 compatible VID with 1% overall system set point accuracy
• Programmable Dynamic VID Slew Rate
• +/-300mV Differential Remote Sense
• Programmable VID Offset Voltage at the Error Amplifier’s Non-Inverting Input allows Zero Offset
• Programmable 150kHz to 1MHz oscillator
• Programmable VID Offset and Load Line output impedance
• Programmable Hiccup Over-Current Protection with Delay to prevent false triggering
• Simplified VR Ready output provides indication of proper operation and avoids false triggering
• Operates from 12V input with 9.9V Under-Voltage Lockout
• 6.8V/6mA Bias Regulator provides System Reference Voltage
• Phase IC Gate Driver Bias Regulator / VRHOT Comparator
• Reduced Over-Current Detect Delay eliminates and external resistor in typical applications
• Small thermally enhanced 28L MLPQ package
Page 1 of 47
9/14/2005
1 page  
IR3084U
PARAMETER
TEST CONDITION
CURRENT SENSE INPUT
IIN BIAS CURRENT
IIN Preconditioning Pull-Down
Resistance
IIN Preconditioning RESET
Threshold
IIN Preconditioning SET
Threshold
V(SS/DEL) > 0.85V, V(EAOUT) > 0.5V
V(SS/DEL) < 0.35V
V(EAOUT)
V(SS/DEL)
VDRP BUFFER AMPLIFIER
Input Offset Voltage
Source Current
Sink Current
Bandwidth (-3dB)
Slew Rate
V(VDRP) – V(IIN), 0.5V < V(IIN) < 5V
0.5V < V(IIN) < 5V
0.5V < V(IIN) < 5V
Note 1
Note 1
VBIAS REGULATOR
Output Voltage
Current Limit
−5mA < I(VBIAS) < 0mA
OVER-CURRENT COMPARATOR
Input Offset Voltage
OCSET Bias Current
1V < V(OCSET) < 5V
SOFT START AND DELAY
Start Delay (TD1)
Soft Start Time (TD2)
VID Sample Delay (TD3)
DVID Slew Time & VRRDY
Delay (TD4+TD5)
PowerGood Delay
OC Delay Time
SS/DEL to FB Input Offset
Voltage
SS/DEL Charge Current
SS/DEL Discharge Current
Charge/Discharge Current
Ratio
OC Discharge Current
Charge Voltage
OC/VRRDY Delay Comparator
Threshold
OC/VRRDY Delay Comparator
Threshold
Delay Comparator Hysteresis
VID Sample Delay
Comparator Threshold
SS/DEL Discharge
Comparator Threshold
RDRP = ∞
RDRP = ∞, Time to reach 1.1V
VR10/VR11 mode only
VR10/VR11 mode only
Opteron/Athlon64 mode. Measured from
Vcore=1.1V to when VRRDY transitions HI.
With FB = 0V, adjust V(SS/DEL) until
EAOUT drives high
Note 1
Relative to Charge Voltage, SS/DEL
rising
Relative to Charge Voltage, SS/DEL
falling
Note 1
VR10/VR11 mode only
MIN
−2.0
5.6
0.20
0.35
−10
−9.0
0.2
1
5
6.6
−35
−10
−53.5
1.2
0.8
0.2
0.5
0.7
150
0.85
40
4
9.5
20
3.6
TYP
−0.2
12.5
0.35
0.60
−2
−6.8
0.85
6
10
6.9
−20
0
−51
1.8
1.8
1.0
1.3
2.3
250
1.3
70
6.5
11.2
40
3.85
80
100
20
3.10
215
MAX UNIT
1.0
19.4
µA
KΩ
0.50 V
0.85 V
6
−4.0
4.1
mV
mA
mA
MHz
V/μs
7.2 V
−6 mA
10
−48.5
mV
μA
2.6
2.8
2.5
2.2
4.7
350
1.5
100
9
12.5
60
4.1
ms
ms
ms
ms
ms
us
V
μA
μA
μA/μA
μA
V
mV
mV
mV
V
mV
Page 5 of 47
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5 Page 
IR3084U
VPEAK (5.0V)
VPHASE4&5 (4.5V)
VPHASE3&6 (3.5V)
VPHASE2&7 (2.5V)
VPHASE1&8 (1.5V)
VVALLEY (1.00V)
50% RAMP
DUTY CYCLE
SLOPE = 80mV / % DC
SLOPE = 1.6mV / ns @ 200kHz
SLOPE = 8.0mV / ns @ 1MHz
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
Figure 4 – 8 Phase Oscillator Waveforms
PWM Operation
The PWM comparator is located in the Phase IC. Upon receiving a clock pulse, the PWM latch is set, the
PWMRMP voltage begins to increase, the low side driver is turned off, and the high side driver is then turned on.
When the PWMRMP voltage exceeds the Error Amp’s output voltage the PWM latch is reset. This turns off the
high side driver, turns on the low side driver, and activates the Ramp Discharge Clamp. The clamp quickly
discharges the PWMRMP capacitor to the VDAC voltage of the Control IC until the next clock pulse.
The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in
response to a load step decrease. Phases can overlap and go to 100% duty cycle in response to a load step
increase with turn-on gated by the clock pulses. An Error Amp output voltage greater than the common mode
input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This
arrangement guarantees the Error Amp is always in control and can demand 0 to 100% duty cycle as required. It
also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of
most systems. The inductor current will increase much more rapidly than decrease in response to load transients.
This control method is designed to provide “single cycle transient response” where the inductor current changes
in response to load transients within a single switching cycle maximizing the effectiveness of the power train and
minimizing the output capacitor requirements. An additional advantage is that differences in ground or input
voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC.
Page 11 of 47
9/14/2005
11 Page | ||
| Páginas | Total 47 Páginas | |
| PDF Descargar | [ Datasheet IR3084U.PDF ] | |
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