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PDF W3EG72255S-D3 Data sheet ( Hoja de datos )

Número de pieza W3EG72255S-D3
Descripción 2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC
Fabricantes White Electronic 
Logotipo White Electronic Logotipo



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White Electronic Designs
W3EG72255S-D3
-JD3
-AJD3
PRELIMINARY*
2GB – 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL
FEATURES
Double-data-rate architecture
DDR200, DDR266 and DDR333:
• JEDEC design specifications
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Dual Rank
Power supply: VCC = 2.5V ± 0.2V
www.DataSheet4U.com
JEDEC standard 184 pin DIMM package
• Package height options:
JD3: 30.48mm (1.2"),
AJD3: 28.70mm (1.13")
DESCRIPTION
The W3EG72255S is a 2x128Mx72 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of eighteen 256Mx4
stacks, in 66 pin TSOP packages mounted on a 184 pin
FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible
on both edges and Burst Lengths allow the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
* wThis product is under development, is not qualified or characterized and is subject
to change without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
DDR333 @CL=2.5
166MHz
2.5-3-3
OPERATING FREQUENCIES
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2
133MHz
2-3-3
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
November 2004
Rev. 2
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 page




W3EG72255S-D3 pdf
White Electronic Designs
W3EG72255S-D3
-JD3
-AJD3
PRELIMINARY
Parameter
Operating Current
Operating Current
Precharge Power-
Down Standby Current
Idle Standby Current
Active Power-Down
Standby Current
Active Standby Current
Operating Current
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C TA +70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V.
Includes DDR SDRAM components only
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7A
Rank 1
Conditions
One device bank; Active - Precharge; tRC
= tRC (MIN); tCK = tCK (MIN); DQ,DM and
DQS inputs changing once per clock cycle;
Address and control inputs changing once
every two cycles.
One device bank; Active-Read-Precharge
Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN);
lOUT = 0mA; Address and control inputs
changing once per clock cycle.
All device banks idle; Power-down mode;
tCK = tCK (MIN); CKE = (low)
CS# = High; All device banks idle;
tCK = tCK (MIN); CKE = High; Address
and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS
and DM.
One device bank active; Power-Down
mode; tCK (MIN); CKE = (low)
CS# = High; CKE = High; One device
bank; Active-Precharge;tRC = tRAS (MAX);
tCK = tCK (MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address
and other control inputs changing once per
clock cycle.
Burst = 2; Reads; Continuous burst; One
device bank active; Address and control
inputs changing once per clock cycle; tCK =
tCK (MIN); lOUT = 0mA.
Burst = 2; Writes; Continuous burst; One
device bank active; Address and control
inputs changing once per clock cycle;
tCK = tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle.
tRC = tRC (MIN)
CKE 0.2V
Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC (MIN);
tCK=tCK(MIN); Address and control inputs
change only during Active Read or Write
commands.
DDR333@CL=2.5
Max
4140
4680
180
1620
1260
1800
4770
4590
7020
180
9090
DDR266:@CL=2, 2.5
Max
4140
4680
180
1620
1260
1800
4770
4590
7020
180
9000
DDR200@CL=2
Max
4140
4680
180
1620
1260
1800
4770
4590
7020
180
9000
Units
mA
Rank 2
Standby
State
IDD3N
mA IDD3N
rnA IDD2P
mA IDD2F
mA IDD3P
mA IDD3N
mA IDD3N
rnA IDD3N
mA IDD3N
mA IDD6
mA IDD3N
November 2004
Rev. 2
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

5 Page





W3EG72255S-D3 arduino
White Electronic Designs
W3EG72255S-D3
-JD3
-AJD3
PRELIMINARY
ORDERING INFORMATION FOR JD3
Part Number
Speed
CAS Latency tRCD
tRP
Height*
W3EG72255S335JD3xG
166MHz/333Mb/s
2.5
3 3 30.48 (1.20")
W3EG72255S262JD3xG
133MHz/266Mb/s
2
2 2 30.48 (1.20")
W3EG72255S263JD3xG
133MHz/266Mb/s
2
3 3 30.48 (1.20")
W3EG72255S265JD3xG
133MHz/266Mb/s
2.5
3 3 30.48 (1.20")
W3EG72255S202JD3xG
100MHz/200Mb/s
2
2 2 30.48 (1.20")
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR JD3
3.99
(0.157 (2x))
17.78
(0.700)
10.0
(0.394)
6.36
(0.250)
133.48
(5.255" MAX.)
131.34
(5.171")
128.95
(5.077")
64.77
(2.550)
6.35
(0.250)
1.78
(0.070)
6.35
(0.250 MAX)
1.27
49.53 (0.050 TYP.)
(1.950)
30.48
(1.20 MAX)
2.31
(0.091)
(2x)
3.99
(0.157)
3.00 (MIN)
(0.118)
(4x)
1.27
± 0.10
(0.050)
(± 0.004)
November 2004
Rev. 2
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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