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PDF W3EG72128S-JD3 Data sheet ( Hoja de datos )

Número de pieza W3EG72128S-JD3
Descripción 1GB - 2x64Mx72 DDR SDRAM UNBUFFERED
Fabricantes White Electronic 
Logotipo White Electronic Logotipo



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White Electronic Designs
W3EG72128S-D3
-JD3
ADVANCED*
1GB – 2x64Mx72 DDR SDRAM UNBUFFERED
FEATURES
Double-data rate architecture
DDR200, DDR266, DDR333 and DDR400
• JEDEC design specifications
BI-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Dual Rank
Power supply:
• VCC = VCCQ = +2.5V ± 0.20V (100, 133, 166MHz)
www.DataSheet4U.com
• VCC = VCCQ = +2.6V ± 0.10V (200MHz)
JEDEC Standard 184 pin DIMM package
• PCB height: 30.48 (1.20")
DESCRIPTION
the W3EG72128S is a 2x64Mx72 Double data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of eighteen 64Mx8
DDR SDRAMs in 66 pin TSOP packages mounted on a
184 pin FR4 substrate.
Synchronous design allows precisse cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
DDR400 @CL=3
200MHz
3-3-3
OPERATING FREQUENCIES
DDR333 @CL=2.5
166MHz
2.5-3-3
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
May 2005
Rev. 3
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 page




W3EG72128S-JD3 pdf
White Electronic Designs
W3EG72128S-D3
-JD3
ADVANCED
IDD SPECIFICATIONS AND TEST CONDITIONS
VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V; DDR400: VCC = VCCQ = 2.6V ± 0.1V
Includes DDR SDRAM component only
Parameter
Symbol Conditions
Operating Current
IDD0 One device bank; Active - Precharge;
tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control
inputs changing once every two
cycles.
Operating Current
IDD1 One device bank; Active-Read-
Precharge Burst = 2; tRC=tRC (MIN);
tCK=tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per
clock cycle.
Precharge Power-
IDD2P All device banks idle; Power-down
Down Standby Current
mode; tCK=tCK (MIN); CKE=(low)
Idle Standby Current
IDD2F CS# = High; All device banks idle;
tCK=tCK (MIN); CKE = high; Address
and other control inputs changing
once per clock cycle. VIN = VREF for
DQ, DQS and DM.
Active Power-Down
Standby Current
IDD3P One device bank active; Power-
Down mode; tCK (MIN); CKE=(low)
Active Standby Current IDD3N CS# = High; CKE = High; One device
bank; Active-Precharge; tRC=tRAS
(MAX); tCK=tCK (MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control
inputs changing once per clock cycle.
Operating Current
IDD4R Burst = 2; Reads; Continuous burst;
One device bank active; Address
and control inputs changing once
per clock cycle; TCK= TCK (MIN); lOUT
= 0mA.
Operating Current
IDD4W Burst = 2; Writes; Continuous burst;
One device bank active; Address
and control inputs changing once per
clock cycle; tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle.
Auto Refresh Current IDD5 tRC = tRC (MIN)
Self Refresh Current
IDD6 CKE 0.2V
Operating Current
IDD7A Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC
(MIN); tCK=tCK (MIN); Address and
control inputs change only during
Active Read or Write commands.
DDR400@
CL=3
Max
2475
2745
90
990
810
1080
2790
2835
4185
90
5130
DDR333@
CL=2.5
Max
2070
2340
90
810
630
900
2385
2475
3510
90
4545
DDR266@
CL=2
Max
2070
2340
90
810
630
900
2385
2475
3510
90
4500
DDR266@
CL=2.5
Max
2070
2340
90
810
630
900
2385
2475
3510
90
4500
DDR200@
CL=2
Max
Units
mA
2070
mA
2340
90 rnA
mA
810
630 mA
mA
900
mA
2385
rnA
2475
3510 mA
90 mA
mA
4500
May 2005
Rev. 3
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

5 Page





W3EG72128S-JD3 arduino
White Electronic Designs
W3EG72128S-D3
-JD3
ADVANCED
ORDERING INFORMATION FOR D3
Part Number
Speed
CAS Latency tRCD
tRP
Height*
W3EG72128S403D3
200MHz/400Mb/s
3
3 3 30.48 (1.20")
W3EG72128S335D3
166MHz/333Mb/s
2.5
3 3 30.48 (1.20")
W3EG72128S262D3
133MHz/266Mb/s
2
2 2 30.48 (1.20")
W3EG72128S265D3
133MHz/266Mb/s
2.5
3 3 30.48 (1.20")
W3EG72128S202D3
100MHz/200Mb/s
2
2 2 30.48 (1.20")
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR D3
3.99
(0.157 (2x))
17.78
(0.700)
10.01
(0.394)
6.35
(0.250)
133.48
(5.255" MAX.)
131.34
(5.171")
128.95
(5.077")
64.77
(2.550)
6.35
(0.250)
1.78
(0.070)
1.27
49.53 (0.050 TYP.)
(1.950)
2.54
(0.100)
30.48
(1.20)
MAX
3.99
(0.157)
(MIN)
2.31
(0.091)
(2x)
3.00
(0.118)
(4x)
1.27 ± 0.10
(0.050 ± 0.004)
May 2005
Rev. 3
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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