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PDF W3EG72128S-BD4 Data sheet ( Hoja de datos )
| Número de pieza | W3EG72128S-BD4 | |
| Descripción | 1GB - 2x64Mx72 DDR SDRAM UNBUFFERED ECC | |
| Fabricantes | White Electronic | |
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White Electronic Designs
W3EG72128S-AD4
-BD4
PRELIMINARY*
1GB – 2x64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL
FEATURES
Double-data-rate architecture
DDR200, DDR266 and DDR333
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Dual Rank
Power supply: 2.5V ± 0.20V
JEDEC standard 200 pin SO-DIMM package
• Package height options:
www.DataSheet4U.com AD4: 35.5 mm (1.38") and
BD4: 31.75 mm (1.25")
DESCRIPTION
The W3EG72128S is a 2x64Mx72 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. This module consists of eighteen 64Mx8 bit
DDR SDRAMs in 66 pin TSOP packages mounted on a
200 pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR333 @CL=2.5
166MHz
2.5-3-3
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
August 2005
Rev. 3
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
W3EG72128S-AD4
-BD4
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Parameter
Symbol Conditions
DDR333@CL=2.5 DDR266@CL=2 DDR266@CL=2.5 DDR200@CL=2
Max Max Max Max
Units
One device bank; Active - Precharge;
tRC=tRC(MIN); tCK=tCK(MIN); DQ,DM
Operating Current
IDD0
and DQS inputs changing once per
clock cycle; Address and control
2620
2620
2620
2620 mA
inputs changing once every two
cycles.
One device bank; Active-Read-
Precharge; Burst = 2; tRC=tRC(MIN)
Operating Current
IDD1 ;tCK=tCK(MIN); Iout = 0mA; Address
2890
2890
2890
2890 mA
and control inputs changing once per
clock cycle.
Precharge Power-
Down Standby Current
IDD2P
All device banks idle; Power- down
mode; tCK=tCK(MIN); CKE=(low)
90
90
90
90 mA
CS# = High; All device banks idle;
tCK=tCK(MIN); CKE = high; Address
Idle Standby Current IDD2F and other control inputs changing
1085
1085
1085
1085 mA
once per clock cycle. Vin = Vref for
DQ, DQS and DM.
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-down
mode; tCK(MIN); CKE=(low)
630
630
630
630 mA
CS# = High; CKE = High; One
device bank; Active-Precharge;
tRC=tRAS(MAX); tCK=tCK(MIN); DQ,
Active Standby Current IDD3N DM and DQS inputs changing twice
1175
1175
1175
1175 mA
per clock cycle; Address and other
control inputs changing once per
clock cycle.
Burst = 2; Reads; Continous burst;
One device bank active;Address
Operating Current
IDD4R and control inputs changing once
2935
2935
2935
2935 mA
per clock cycle; tCK=tCK(MIN); Iout
= 0mA.
Burst = 2; Writes; Continous burst;
One device bank active; Address
Operating Current
IDD4W
and control inputs changing once per
clock cycle; tCK=tCK(MIN); DQ,DM
3025
2845
2845
2845 mA
and DQS inputs changing twice per
clock cycle.
Auto Refresh Current IDD5 tRC=tRC(MIN)
4060 4060 4060 4060 mA
Self Refresh Current
IDD6 CKE ≤ 0.2V
360 365 365 365 mA
Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC
Operating Current
IDD7A (MIN); tCK=tCK(MIN); Address and
5095
5050
5050
5050 mA
control inputs change only during
Active Read or Write commands.
August 2005
Rev. 3
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page 
White Electronic Designs
W3EG72128S-AD4
-BD4
PRELIMINARY
ORDERING INFORMATION FOR BD4
Part Number
Speed
CAS Latency tRCD
tRP
Height*
W3EG72128S335BD4-xG
166MHz/333Mb/s
2.5
3 3 31.75 (1.25")
W3EG72128S262BD4-xG
133MHz/266Mb/s
2
2 2 31.75 (1.25")
W3EG72128S265BD4-xG
133MHz/266Mb/s
2.5
3 3 31.75 (1.25")
W3EG72128S202BD4-xG
100MHz/200Mb/s
2
2 2 31.75 (1.25")
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “-x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR BD4
3.98 ± 0.1
(0.157 ± 0.004)
67.56
(2.666) MAX
2.31
(0.091) REF.
11.40
(0.449)
4.19
(0.165)
1.80
(0.071)
47.40
(1.866)
6.35
(0.250) MAX.
31.75
(1.25)
20
(0.787)
3.99
(0.157) MIN.
0.99 ± 0.10
(0.039 ± 0.004)
* ALL DIMENSIONS ARE IN MILIMETERS AND (INCHES)
August 2005
Rev. 3
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
11 Page | ||
| Páginas | Total 14 Páginas | |
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