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PDF W3EG6466S-AD4 Data sheet ( Hoja de datos )
| Número de pieza | W3EG6466S-AD4 | |
| Descripción | 512MB - 2x32Mx64 DDR SDRAM UNBUFFERED | |
| Fabricantes | White Electronic | |
| Logotipo |  |
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White Electronic Designs
W3EG6466S-AD4
-BD4
PRELIMINARY*
512MB – 2x32Mx64 DDR SDRAM UNBUFFERED, w/PLL
FEATURES
DDR200, DDR266 and DDR333
• JEDEC design specifications
Double-data-rate architecture
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Dual Rank
Power supply: 2.5V ± 0.20V
JEDECwww.DataSheet4U.com standard 200 pin SO-DIMM package
• Package height options:
AD4: 35.5mm (1.38")
BD4: 31.75mm (1.25")
DESCRIPTION
The W3EG6466S is a 2x32Mx64 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of sixteen 32Mx8
components as eight 64Mx8 stacked DDR SDRAMs
in 66 pin TSOP packages mounted on a 200 pin FR4
substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR333 @CL=2.5
166MHz
2.5-3-3
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 2
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
W3EG6466S-AD4
-BD4
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ±0.2V, VCC = 2.5V ±0.2V
DDR333@CL=2.5 DDR266@CL=2, 2.5 DDR200@CL=2
Parameter
Symbol Conditions
Max Max Max
One device bank; Active - Precharge;
1600 1440 1360
tRC=tRC(MIN); tCK=tCK(MIN); DQ,DM and DQS
Operating Current
IDD0 inputs changing once per clock cycle; Address
and control inputs changing once every two
cycles.
One device bank; Active-Read-Precharge;
1800
1640
1560
Operating Current
IDD1
Burst = 2; tRC=tRC(MIN);tCK=tCK(MIN); Iout =
0mA; Address and control inputs changing
once per clock cycle.
Precharge Power-Down
Standby Current
IDD2P
All device banks idle; Power- down mode;
tCK=tCK(MIN); CKE=(low)
48
48
48
CS# = High; All device banks idle;
400 320 320
Idle Standby Current
IDD2F
tCK=tCK(MIN); CKE = high; Address and other
control inputs changing once per clock cycle.
Vin = Vref for DQ, DQS and DM.
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-down mode;
tCK(MIN); CKE=(low)
560
480
480
CS# = High; CKE = High; One device
880 720 720
bank; Active-Precharge; tRC=tRAS(MAX);
Active Standby Current
IDD3N
tCK=tCK(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address and
other control inputs changing once per clock
cycle.
Burst = 2; Reads; Continous burst; One 2160 1840 1840
Operating Current
IDD4R
device bank active;Address and control inputs
changing once per clock cycle; tCK=tCK(MIN);
Iout = 0mA.
Burst = 2; Writes; Continous burst; One
2160 1800 1800
device bank active; Address and control inputs
Operating Current
IDD4W changing once per clock cycle; tCK=tCK(MIN);
DQ,DM and DQS inputs changing twice per
clock cycle.
Auto Refresh Current
IDD5 tRC=tRC(MIN)
2240 2000 2000
Self Refresh Current
IDD6 CKE ≤ 0.2V
48 48 48
Four bank interleaving Reads (BL=4) with auto
3120
2960
2720
Operating Current
IDD7A
precharge with tRC=tRC (MIN); tCK=tCK(MIN);
Address and control inputs change only
during Active Read or Write commands.
* For DDR333 consult factory
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 2
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page 
White Electronic Designs
W3EG6466S-AD4
-BD4
PRELIMINARY
ORDERING INFORMATION FOR AD4
Part Number
Speed
Height*
W3EG6466S335AD4
166MHz/333Mbps, CL=2.5
35.5 (1.38)
W3EG6466S262AD4
133MHz/266Mbps, CL=2
35.5 (1.38)
W3EG6466S265AD4
133MHz/266Mbps, CL=2.5
35.5 (1.38)
W3EG6466S202AD4
100MHz/200Mbps, CL=2
35.5 (1.38)
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR AD4
3.98 ± 0.1
(0.157 ± 0.004)
2.0
(0.079)
67.56
(2.666) MAX.
P1
2.31
(0.091) REF.
11.40
(0.449)
4.19
(0.165)
1.80
(0.071)
47.40
(1.866)
6.35
(0 .250)
MAX.
35.05
(1.38) MAX.
20
(0.787)
3.98
(0.157) MIN.
1.0 ± 0.1
(0.039 ± 0.004)
* ALL DIMENSIONS ARE IN MILIMETERS AND (INCHES)
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 2
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet W3EG6466S-AD4.PDF ] | |
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