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PDF W3EG6465S-D4 Data sheet ( Hoja de datos )

Número de pieza W3EG6465S-D4
Descripción 512MB- 64Mx64 DDR SDRAM UNBUFFERED
Fabricantes White Electronic 
Logotipo White Electronic Logotipo



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White Electronic Designs
W3EG6465S-D4
PRELIMINARY*
512MB- 64Mx64 DDR SDRAM UNBUFFERED
FEATURES
Double-data-rate architecture
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Power Supply: 2.5V ± 0.20V
JEDEC standard 200 pin SO-DIMM package
DESCRIPTION
The W3EG6465S is a 64Mx64 Double Data Rate
SDRAM memory module based on 512Mb DDR
SDRAM component. The module consists of eight
64Mx8 DDR SDRAMs in 66 pin TSOP package
mounted on a 200 Pin FR4 substrate.
Synchronous design allows precise cycle control with
the use of system clock. Data I/O transactions are
possible on both edges and Burst Lenths allow the
same device to be useful for a variety of high bandwidth,
high performance memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
www.DataSheet4U.com
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR266 @CL=2
133MHz
2-3-3
DDR200 @CL=2
100MHz
2-2-2
May 2004
Rev. 3
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 page




W3EG6465S-D4 pdf
White Electronic Designs
W3EG6465S-D4
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C TA 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Parameter
Symbol Conditions
DDR266@CL=2 DDR266@CL=2.5 DDR266@CL=2 DDR200@CL=2
Max Max Max Max Units
2-2-2 2.5-3-3 2-3-3
2-2-2
One device bank; Active - Precharge;
tRC=tRC(MIN); tCK=tCK(MIN); DQ,DM
Operating Current IDD0 and DQS inputs changing once per
1320 1320 1320 1320 mA
clock cycle; Address and control inputs
changing once every two cycles.
One device bank; Active-Read-Precharge;
Operating Current
IDD1
Burst = 2; tRC=tRC(MIN);tCK=tCK(MIN);
Iout = 0mA; Address and control inputs
1520
1520
1520
1520 mA
changing once per clock cycle.
Precharge Power-
Down Standby
Current
IDD2P
All device banks idle; Power- down mode;
tCK=tCK(MIN); CKE=(low)
48
48
48
48 mA
CS# = High; All device banks idle;
Idle Standby
Current
tCK=tCK(MIN); CKE = high; Address and
IDD2F other control inputs changing once per
clock cycle. Vin = Vref for DQ, DQS and
400
400
400
400 mA
DM.
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-down
mode; tCK(MIN); CKE=(low)
400
400
400
400 mA
CS# = High; CKE = High; One device
bank; Active-Precharge; tRC=tRAS(MAX);
Active Standby
Current
IDD3N
tCK=tCK(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address
760
760
760
760 mA
and other control inputs changing once
per clock cycle.
Burst = 2; Reads; Continous burst; One
Operating Current
IDD4R
device bank active;Address and control
inputs changing once per clock cycle;
1760
1760
1760
1760 mA
tCK=tCK(MIN); Iout = 0mA.
Burst = 2; Writes; Continous burst; One
device bank active; Address and control
Operating Current IDD4W inputs changing once per clock cycle;
2000
2000
2000
2000 mA
tCK=tCK(MIN); DQ,DM and DQS inputs
changing twice per clock cycle.
Auto Refresh
Current
IDD5 tRC=tRC(MIN)
2480 2480 2480 2480 mA
Self Refresh
Current
IDD6 CKE 0.2V
40 40 40 40 mA
Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC (MIN);
Operating Current IDD7A tCK=tCK(MIN); Address and control inputs
3840
3840
3840
3840 mA
change only during Active Read or Write
commands.
May 2004
Rev. 3
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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