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Datasheet W3EG6433S Equivalent ( PDF ) |
| N.º | Número de pieza | Descripción | Fabricantes | Category |
| 1 | W3EG6433S-AD4 | 256MB - 32Mx64 DDR SDRAM UNBUFFERED White Electronic Designs
W3EG6433S-AD4 -BD4
PRELIMINARY*
256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL
FEATURES
DDR200, DDR266 and DDR333 Double-data-rate architecture Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Len |  White Electronic | buffer |
| 2 | W3EG6433S-BD4 | 256MB - 32Mx64 DDR SDRAM UNBUFFERED White Electronic Designs
W3EG6433S-AD4 -BD4
PRELIMINARY*
256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL
FEATURES
DDR200, DDR266 and DDR333 Double-data-rate architecture Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Len | White Electronic | buffer |
| 3 | W3EG6433S-D3 | 256MB - 2x16Mx64 DDR SDRAM UNBUFFERED White Electronic Designs
W3EG6433S-D3 -JD3
PRELIMINARY*
256MB – 2x16Mx64 DDR SDRAM UNBUFFERED
FEATURES
DDR266 and DDR333 Double-data-rate architecture Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) | White Electronic | buffer |
| 4 | W3EG6433S-JD3 | 256MB - 2x16Mx64 DDR SDRAM UNBUFFERED White Electronic Designs
W3EG6433S-D3 -JD3
PRELIMINARY*
256MB – 2x16Mx64 DDR SDRAM UNBUFFERED
FEATURES
DDR266 and DDR333 Double-data-rate architecture Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) | White Electronic | buffer |
W3E Datasheet ( Hoja de datos ) - resultados coincidentes |
| N.º | Número de pieza | Descripción | Fabricantes | Catagory |
| 1 | W3E16M64S-XBX | 16Mx64 DDR SDRAM White Electronic Designs
16Mx64 DDR SDRAM
FEATURES
DDR Data Rate = 200, 250, 266Mbps Package: • 219 Plastic Ball Grid Array (PBGA), 21 x 25mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CLK and CLK#) Commands entered on each positive CLK edge Internal pipe White Electronic data | | |
| 2 | W3E16M72S-XBX | 16Mx72 Registered DDR SDRAM White Electronic Designs
16Mx72 Registered DDR SDRAM
FEATURES
Registered for enhanced performance of bus speeds of 200, 225, and 250 MHz Package: • 219 Plastic Ball Grid Array (PBGA), 32 x 25mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CK and CK#) Comman White Electronic register | | |
| 3 | W3E16M72SR-XBX | 16Mx72 Registered DDR SDRAM White Electronic Designs
16Mx72 Registered DDR SDRAM
FEATURES
Registered for enhanced performance of bus speeds of 200, 225, and 250 MHz Package: • 219 Plastic Ball Grid Array (PBGA), 32 x 25mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CK and CK#) Comman White Electronic register | | |
| 4 | W3E232M16S-XSTX | 2x32Mx16bit DDR SDRAM White Electronic Designs
2x32Mx16bit DDR SDRAM
FEATURES
Double-data-rate architecture; two data transfers per clock cycle Data rate = 200, 266, 333, 400 Mbs Package: • 66pin TSOP II package 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs(CK and CK#) DLL aligns White Electronic data | | |
| 5 | W3E32M64S-XBX | 32Mx64 DDR SDRAM White Electronic Designs
32Mx64 DDR SDRAM
FEATURES
DDR SDRAM rate = 200, 250, 266, 333Mb/s Package: • 219 Plastic Ball Grid Array (PBGA), 25mm x 25mm, 625mm2
W3E32M64S-XBX
BENEFITS
41% SPACE SAVINGS vs. TSOP Reduced part count Reduced trace lengths for l White Electronic data | | |
| 6 | W3E32M64S-XSBX | 32Mx64 DDR SDRAM White Electronic Designs
32Mx64 DDR SDRAM
FEATURES
DDR SDRAM rate = 200, 250, 266, 333** Package: • 208 Plastic Ball Grid Array (PBGA), 13 x 22mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CK and CK#) Commands entered on each po White Electronic data | | |
| 7 | W3E32M72S-XBX | 32Mx72 DDR SDRAM White Electronic Designs
32Mx72 DDR SDRAM
FEATURES
Data rate = 200, 250, 266, 333Mbs Package: • 219 Plastic Ball Grid Array (PBGA), 32 x 25mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CK and CK#) Commands entered on each positive CK edge Internal pipelin White Electronic data | |
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