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PDF W3EG6432S-D3 Data sheet ( Hoja de datos )

Número de pieza W3EG6432S-D3
Descripción 32Mx64 DDR SDRAM UNBUFFERED
Fabricantes White Electronic 
Logotipo White Electronic Logotipo



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No Preview Available ! W3EG6432S-D3 Hoja de datos, Descripción, Manual

White Electronic Designs
W3EG6432S-D3
-JD3
PRELIMINARY*
256MB – 32Mx64 DDR SDRAM UNBUFFERED
FEATURES
Double-data-rate architecture
DDR200, DDR266, DDR333 and DDR400
• JEDEC design specifications
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Power supply:
• VCC = VCCQ = +2.5V ±0.2V (100, 133 and
166MHz)
www.DataSheet4U.com
• VCC
=
VCCQ
=
+2.6V
±0.1V
(200MHz)
JEDEC standard 184 pin DIMM package
• JD3 PCB height: 30.48 (1.20") max
DESCRIPTION
The W3EG6432S is a 32Mx64 Double Data Rate
SDRAM memory module based on 256Mb DDR SDRAM
components. The module consists of eight 32Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
• Lead-free products
• Vendor source control option
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR400 @CL=3
200MHz
3-3-3
DDR333 @CL=2.5
166MHz
2.5-3-3
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2
133MHz
2-3-3
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
May 2005
Rev. 6
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 page




W3EG6432S-D3 pdf
White Electronic Designs
W3EG6432S-D3
-JD3
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C TA 70°C, VCC = VCCQ = 2.5V ± 0.2V, VCC = VCCQ = 2.6V ± 0.1V (200MHz)V
Includes DDR SDRAM component only
Parameter
Operating Current
Operating Current
Precharge Power-
Down Standby
Current
Idle Standby Current
Active Power-Down
Standby Current
Active Standby
Current
Operating Current
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current
Symbol
IDD0
IDD1
IDD2P
Conditions
One device bank; Active - Precharge;
tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control inputs
changing once every two cycles.
One device bank; Active-Read-
Precharge Burst = 2; tRC=tRC (MIN);
tCK=tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per
clock cycle.
All device banks idle; Power-down
mode; tCK=tCK (MIN); CKE=(low)
DDR400@
CL=3
Max
1080
1360
32
DDR333@
CL=2.5-3-3
Max
1000
1360
32
DDR266@
CL=2
Max
1000
1200
32
IDD2F CS# = High; All device banks idle;
480 400 360
tCK=tCK (MIN); CKE = high; Address
and other control inputs changing once
per clock cycle. VIN = VREF for DQ,
DQS and DM.
IDD3P One device bank active; Power-Down
320
240
200
mode; tCK (MIN); CKE=(low)
IDD3N CS# = High; CKE = High; One device
560
480
400
bank; Active-Precharge; tRC=tRAS
(MAX); tCK=tCK (MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control inputs
changing once per clock cycle.
IDD4R Burst = 2; Reads; Continuous burst; 1600 1400 1200
One device bank active; Address and
control inputs changing once per clock
cycle; TCK= TCK (MIN); lOUT = 0mA.
IDD4W Burst = 2; Writes; Continuous burst; 1560 1400 1200
One device bank active; Address and
control inputs changing once per clock
cycle; tCK=tCK (MIN); DQ,DM and DQS
inputs changing once per clock cycle.
IDD5 tRC = tRC (MIN)
2080 2040 1880
IDD6 CKE 0.2V
32 32 32
IDD7A Four bank interleaving Reads (BL=4)
3760
3280
2800
with auto precharge with tRC=tRC (MIN);
tCK=tCK (MIN); Address and control
inputs change only during Active Read
or Write commands.
DDR266@
CL=2.5
Max
1000
1200
32
360
200
400
1200
1200
1880
32
2800
DDR200@
CL=2
Max
1000
1200
32
360
200
400
1200
1200
1880
32
2800
Units
mA
mA
rnA
mA
mA
mA
mA
rnA
mA
mA
mA
May 2005
Rev. 6
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

5 Page





W3EG6432S-D3 arduino
White Electronic Designs
W3EG6432S-D3
-JD3
PRELIMINARY
ORDERING INFORMATION FOR JD3
Part Number
W3EG6432S403JD3
Speed
200MHz/400Mb/s
CAS Latency tRCD
33
tRP
3
Height*
30.48 (1.20")
Temperature
0°C to 70°C
W3EG6432S335JD3
166MHz/333Mb/s
2.5 3 3 30.48 (1.20")
0°C to 70°C
W3EG6432S262JD3
133MHz/266Mb/s
2
22
30.48 (1.20")
0°C to 70°C
W3EG6432S263JD3
133MHz/266Mb/s
2
33
30.48 (1.20")
0°C to 70°C
W3EG6432S265JD3
133MHz/266Mb/s
2.5 3 3 30.48 (1.20")
0°C to 70°C
W3EG6432S202JD3
100MHz/200Mb/s
2
22
30.48 (1.20")
0°C to 70°C
NOTE:
1 * Consult Factory for availability of lead-free products. (F = Lead-Free, G = RoHS Compliant)
2 * Product specific part numbers are available for source control if needed, please consult factory for the correct part number if a specific component vendor is preferred.
3 * Consult factory for availability for industrial temperature (-40°C to 85°C) options
3.99
(0.157 (2x))
17.78
(0.700)
10.01
(0.394)
6.35
(0.250)
PACKAGE DIMENSIONS FOR JD3
133.48
(5.255" MAX.)
131.34
(5.171")
128.95
(5.077")
64.77
(2.550)
6.35
(0.250)
1.78
(0.070)
1.27
49.53 (0.050 TYP.)
(1.950)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
2.54
(0.100 MAX)
30.48
(1.20)
MAX
3.99
(0.157)
(MIN)
2.31
(0.091)
(2x)
3.00
(0.118)
(4x)
1.27 ± 0.10
(0.050 ± 0.004)
May 2005
Rev. 6
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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