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PDF W3EG264M72AFSRXXXD3 Data sheet ( Hoja de datos )
| Número de pieza | W3EG264M72AFSRXXXD3 | |
| Descripción | 1GB - 2x64Mx72 DDR SDRAM REGISTERED ECC | |
| Fabricantes | White Electronic | |
| Logotipo |  |
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White Electronic Designs W3EG264M72AFSRxxxD3
ADVANCED*
1GB – 2x64Mx72 DDR SDRAM REGISTERED ECC w/PLL, FBGA
FEATURES
Double-data-rate architecture
DDR200, DDR266 and DDR333:
• JEDEC design specifications
Phase-lock loop (PLL) clock driver to reduce
loading
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Dual Rank
Powerwww.DataSheet4U.com supply: VCC 2.5V ± 0.2V
JEDEC standard 184 pin DIMM package
• Package height option:
Low-profile: 30.48mm (1.20")
• Consult factory for availability of lead-free
products.
DESCRIPTION
The W3EG264M72AFSR is a 2x64Mx72 Double Data Rate
SDRAM memory module based on 256Mb DDR SDRAM
components. The module consists of thirtysix 64Mx4, in
FBGA packages mounted on a 184 pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
DDR333 @CL=2.5
166MHz
2.5-3-3
OPERATING FREQUENCIES
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2
133MHz
2-3-3
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
November 2004
Rev. 1
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs W3EG264M72AFSRxxxD3
ADVANCED
Parameter
Operating Current
Operating Current
Precharge Power-
Down Standby Current
Idle Standby Current
Active Power-Down
Standby Current
Active Standby Current
Operating Current
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ +70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V.
Includes DDR SDRAM components only
Rank 1
Symbol Conditions
IDD0 One device bank; Active - Precharge; tRC
= tRC (MIN); tCK = tCK (MIN); DQ,DM and
DQS inputs changing once per clock cycle;
Address and control inputs changing once
every two cycles.
IDD1 One device bank; Active-Read-Precharge
Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN);
lOUT = 0mA; Address and control inputs
changing once per clock cycle.
IDD2P All device banks idle; Power-down mode;
tCK = tCK (MIN); CKE = (low)
IDD2F CS# = High; All device banks idle;
tCK = tCK (MIN); CKE = High; Address
and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS
and DM.
IDD3P One device bank active; Power-Down
mode; tCK (MIN); CKE = (low)
IDD3N CS# = High; CKE = High; One device
bank; Active-Precharge;tRC = tRAS (MAX);
tCK = tCK (MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address
and other control inputs changing once per
clock cycle.
IDD4R Burst = 2; Reads; Continuous burst; One
device bank active; Address and control
inputs changing once per clock cycle; tCK =
tCK (MIN); lOUT = 0mA.
IDD4W Burst = 2; Writes; Continuous burst; One
device bank active; Address and control
inputs changing once per clock cycle;
tCK = tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle.
IDD5 tRC = tRC (MIN)
IDD6 CKE ≤ 0.2V
IDD7A Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC (MIN);
tCK=tCK(MIN); Address and control inputs
change only during Active Read or Write
commands.
DDR333@CL=2.5
Max
4410
5220
144
1800
1080
2160
5310
5040
6750
144
9540
DDR266:@CL=2, 2.5
Max
4050
4680
144
1620
900
1800
4500
4230
6030
144
8100
DDR200@CL=2
Max
4050
4680
144
1620
900
1800
4500
4230
6030
144
8100
Units
mA
Rank 2
Standby
State
IDD3N
mA IDD3N
rnA IDD2P
mA IDD2F
mA IDD3P
mA IDD3N
mA IDD3N
rnA IDD3N
mA IDD3N
mA IDD6
mA IDD3N
November 2004
Rev. 1
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page 
White Electronic Designs W3EG264M72AFSRxxxD3
ADVANCED
ORDERING INFORMATION FOR D3
Part Number
Speed
CAS Latency tRCD tRP
Height*
W3EG264M72AFSR335D3xG
166MHz/333Mb/s
2.5
3 3 30.48 (1.20") MAX
W3EG264M72AFSR262D3xG
133MHz/266Mb/s
2
2 2 30.48 (1.20") MAX
W3EG264M72AFSR263D3xG
133MHz/266Mb/s
2
3 3 30.48 (1.20") MAX
W3EG264M72AFSR265D3xG
133MHz/266Mb/s
2.5
3 3 30.48 (1.20") MAX
W3EG264M72AFSR202D3xG
100MHz/200Mb/s
2
2 2 30.48 (1.20") MAX
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be
replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
2.00
(0.079) R
(4X)
2.50
(0.098) D
(2X)
2.30
(0.091)
TYP.
2.30
(0.091)
TYP.
PIN 1
LOW-PROFILE D3 184-PIN DDR DIMM DIMENSIONS
FRONT VIEW
133.50 (5.255)
3.81 (0.150)
MAX
0.90 (0.035) R
1.27 (0.050)
1.02 (0.040)
TYP.
TYP.
64.77 (2.55)
6.35 (0.250) TYP.
49.53 (1.95)
120.65 (4.750)
BACK VIEW
17.78
(0.700)
TYP.
30.48
(1.20)
MAX
10.00 (0.394)
TYP.
PIN 92
1.37 (0.054)
PIN 184
November 2004
Rev. 1
PIN 93
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet W3EG264M72AFSRXXXD3.PDF ] | |
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