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PDF W3EG2128M72AFSR-D3 Data sheet ( Hoja de datos )

Número de pieza W3EG2128M72AFSR-D3
Descripción 2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC
Fabricantes White Electronic 
Logotipo White Electronic Logotipo



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W3EG2128M72AFSR-D3
White Electronic Designs
-AD3
FINAL*
2GB – 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL, FBGA
FEATURES
Double-data-rate architecture
DDR266, DDR333, and DDR400
Bi-directional data strobes (DQS)
Phase-lock loop (PLL) clock driver to reduce
loading
Differential clock inputs (CK & CK#)
ECC error detection and correction
Programmable Read Latency 2, 2.5 (clock)
Programmable Burst Length (2, 4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Dual Rank
RoHSwww.DataSheet4U.com compliant products
Power Supply:
• VCC = VCCQ = +2.5V ± 0.2 (133 and 166MHz)
• VCC = VCCQ = +2.6V ± 0.1 (200MHz)
JEDEC standard 184 pin DIMM package
• Package height options:
Low-profile: 30.48mm (1.20") MAX
DESCRIPTION
The W3EG2128M72AFSR is a 2x128Mx72 Double Data
Rate SDRAM memory module based on 512Mb DDR
SDRAM components. The module consists of thirtysix
128Mx4 components, in FBGA packages mounted on a
184 pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is subject to change without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
DDR400@CL=3
200MHz
3-3-3
OPERATING FREQUENCIES
DDR333@CL=2.5
166MHz
2.5-3-3
DDR266@CL=2
133MHz
2-2-2
DDR266@CL=2
133MHz
2-3-3
DDR266@CL=2.5
133MHz
2.5-3-3
January 2006
Rev. 3
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 page




W3EG2128M72AFSR-D3 pdf
W3EG2128M72AFSR-D3
White Electronic Designs
-AD3
FINAL
ICC SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C TA +70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V.
Includes DDR SDRAM components only
Parameter
Rank 1
Symbol Conditions
DDR400@CL=3
Max
Operating Current
ICC0 One device bank; Active - Precharge; tRC = tRC (MIN);
tCK = tCK (MIN); DQ,DM and DQS inputs changing
once per clock cycle; Address and control inputs
changing once every two cycles.
3870
Operating Current
ICC1 One device bank; Active-Read-Precharge Burst = 2;
tRC = tRC (MIN); tCK = tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per clock cycle.
4410
Precharge Power-
Down Standby
Current
ICC2P All device banks idle; Power-down mode; tCK = tCK
(MIN); CKE = (low)
180
Idle Standby
Current
ICC2F CS# = High; All device banks idle;
tCK = tCK (MIN); CKE = High; Address and other
control inputs changing once per clock cycle. VIN =
VREF for DQ, DQS and DM.
1980
Active Power-Down ICC3P One device bank active; Power-Down mode; tCK
Standby Current
(MIN); CKE = (low)
1620
Active Standby
Current
ICC3N CS# = High; CKE = High; One device bank; Active-
Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ,
DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per
clock cycle.
2160
Operating Current
ICC4R Burst = 2; Reads; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); lOUT = 0mA.
4500
Operating Current
ICC4W Burst = 2; Writes; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle.
4590
Auto Refresh
Current
ICC5 tRC = tRC (MIN)
7290
Self Refresh
Current
ICC6 CKE 0.2V
180
Operating Current
Note:
ICC 7A
Four bank interleaving Reads (BL=4) with auto
precharge with tRC=tRC (MIN); tCK=tCK(MIN); Address
and control inputs change only during Active Read or
Write commands.
9180
• These parameters serve to support both SAMSUNG and MICRON components based modules.
DDR333@CL=2.5
Max
2780
3780
180
1620
1260
1800
3870
4050
6120
180
8190
DDR266@CL=2,
2.5
Max
2790
3780
180
1620
1260
1800
3870
3690
6120
180
8100
Units
mA
mA
rnA
mA
mA
mA
mA
rnA
mA
mA
mA
Rank 2
Standby
State
ICC3N
ICC3N
ICC2P
ICC2F
ICC3P
ICC3N
ICC3N
ICC3N
ICC3N
ICC6
ICC3N
January 2006
Rev. 3
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

5 Page





W3EG2128M72AFSR-D3 arduino
W3EG2128M72AFSR-D3
White Electronic Designs
-AD3
FINAL
ORDERING INFORMATION FOR AD3
Part Number
Speed/Data Rate CAS Latency tRCD tRP
Height*
W3EG2128M72AFSR403AD3xG
200MHz/400Mb/s
3
3 3 30.48 (1.20") MAX
W3EG2128M72AFSR335AD3xG
166MHz/333Mb/s
2.5
3 3 30.48 (1.20") MAX
W3EG2128M72AFSR262AD3xG
133MHz/266Mb/s
2
2 2 30.48 (1.20") MAX
W3EG2128M72AFSR263AD3xG
133MHz/266Mb/s
2
3 3 30.48 (1.20") MAX
W3EG2128M72AFSR265AD3xG
133MHz/266Mb/s
2.5
3 3 30.48 (1.20") MAX
NOTES:
• RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be
replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
• In an effort to support our customer’s traceability and control requirements (which enables them to quickly identify component speed grades used on modules in the field); WEDC
has created a “26A” module part number option. The W3EG2128M72AFSR26AAD3xG product part number meets all the requirements of the W3EG2128M72AFSR265AD3xG
product however it is built using 400Mhz rated components. We recommend therefore that customers include both the “26A” and “265” final part numbers on their AVL in order to
support flexibility of sourcing and to allow for the best module sourcing lead times. For those customers who wish to allow both sourcing options but only would like to include one
product part number on their AVL, WEDC can accommodate. Please consult factory for more details.
LOW-PROFILE AD3 184-PIN DDR DIMM DIMENSIONS
FRONT VIEW
133.20 (5.255)
3.81 (0.150)
MAX
2.00
(0.079) R
(4x)
2.50
(0.098) D
(2X)
2.30
(0.091)
TYP.
2.30
(0.091)
TYP.
PIN 1
0.90 (0.035) R
1.27 (0.050)
1.02 (0.040)
TYP.
TYP.
64.77 (2.55)
6.35 (0.250) TYP.
49.53 (1.95)
120.65 (4.750)
BACK VIEW
30.48 (1.2)
MAX
17.78 (0.700)
TYP.
10.00 (0.394)
TYP.
PIN 92
1.37 (0.054)
PIN 184
January 2006
Rev. 3
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).
PIN 93
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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