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PDF W3E32M72S-XSBX Data sheet ( Hoja de datos )

Número de pieza W3E32M72S-XSBX
Descripción 32Mx72 DDR SDRAM
Fabricantes White Electronic 
Logotipo White Electronic Logotipo



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No Preview Available ! W3E32M72S-XSBX Hoja de datos, Descripción, Manual

White Electronic Designs
W3E32M72S-XSBX
32Mx72 DDR SDRAM
FEATURES
„ Data rate = 200, 250, 266, 333Mbs
„ Package:
• 208 Plastic Ball Grid Array (PBGA), 16 x 22mm
„ 2.5V ±0.2V core power supply
„ 2.5V I/O (SSTL_2 compatible)
„ Differential clock inputs (CK and CK#)
„ Commands entered on each positive CK edge
„ Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
„ Programmable Burst length: 2,4 or 8
„ Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (one per byte)
„ DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
„ DLLwww.DataSheet4U.com to align DQ and DQS transitions with CK
„ Four internal banks for concurrent operation
„ Data mask (DM) pins for masking write data
(one per byte)
„ Programmable IOL/IOH option
„ Auto precharge option
„ Auto Refresh and Self Refresh Modes
„ Commercial, Industrial and Military
TemperatureRanges
„ Organized as 32M x 72
„ Weight: W3E32M72S-XSBX - 2.5 grams typical
* This product is subject to change without notice.
BENEFITS
„ 73% Space Savings vs. TSOP
• 44% Space Savings vs FPBGA
„ Reduced part count
„ 37% I/O reduction vs TSOP
• 31% I/O reduction vs FPBGA
„ Reduced trace lengths for lower parasitic
capacitance
„ Suitable for hi-reliability applications
„ Laminate interposer for optimum TCE match
„ Upgradeable to 64M x 72 density (contact factory
for information)
GENERAL DESCRIPTION
The 256MByte (2Gb) DDR SDRAM is a high-speed CMOS,
dynamic random-access, memory using 5 chips containing
536,870,912 bits. Each chip is internally configured as a
quad-bank DRAM.
The 256MB DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 256MB DDR SDRAM effectively consists
of a single 2n-bit wide, one-clock-cycle data tansfer at the
internal DRAM core and two corresponding n-bit wide,
one-half-clock-cycle data transfers at the I/O pins.
A bi-directional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at the
receiver.strobe transmitted by the DDR SDRAM during
READs and by the memory contoller during WRITEs. DQS
is edge-aligned with data for READs and center-aligned
with data for WRITEs. Each chip has two data strobes, one
for the lower byte and one for the upper byte.
The 256MB DDR SDRAM operates from a differential clock
(CK and CK#); the crossing of CK going HIGH and CK#
going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered
at every positive edge of CK. Input data is registered on
both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
White Electronic Designs Corp. reserves the right to change products or specications without notice.
July 2006
Rev. 6
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 page




W3E32M72S-XSBX pdf
White Electronic Designs
W3E32M72S-XSBX
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to dene the specic mode of
operation of the DDR SDRAM. This denition includes the
selection of a burst length, a burst type, a CAS latency,
and an operating mode, as shown in Figure 3. The Mode
Register is programmed via the MODE REGISTER SET
command (with BA0 = 0 and BA1 = 0) and will retain
the stored information until it is programmed again or
the device loses power. (Except for bit A8 which is self
clearing).
Reprogramming the mode register will not alter the contents
of the memory, provided it is performed correctly. The Mode
Register must be loaded (reloaded) when all banks are
idle and no bursts are in progress, and the controller must
wait the specied time before initiating the subsequent
operation. Violating either of these requirements will result
in unspecied operation.
Mode register bits A0-A2 specify the burst length, A3
species the type of burst (sequential or interleaved),
A4-A6 specify the CAS latency, and A7-A12 specify the
operating mode.
BURST LENGTH
Read and write accesses to the DDR SDRAM are burst
oriented, with the burst length being programmable,
as shown in Figure 3. The burst length determines
the maximum number of column locations that can be
accessed for a given READ or WRITE command. Burst
lengths of 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-Ai when the burst length is set to two; by A2-Ai when the
burst length is set to four (where Ai is the most signicant
column address for a given conguration); and by A3-Ai
when the burst length is set to eight. The remaining (least
signicant) address bit(s) is (are) used to select the starting
location within the block. The programmed burst length
applies to both READ and WRITE bursts.
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
READ LATENCY
The READ latency is the delay, in clock cycles, between
the registration of a READ command and the availability
of the rst bit of output data. The latency can be set to 2
or 2.5 clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n+m. Table 2 below indicates the operating frequencies at
which each CAS latency setting can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
OPERATING MODE
The normal operating mode is selected by issuing a MODE
REGISTER SET command with bits A7-A12 each set to
zero, and bits A0-A6 set to the desired values. A DLL reset
is initiated by issuing a MODE REGISTER SET command
with bits A7 and A9-A12 each set to zero, bit A8 set to one,
and bits A0-A6 set to the desired values. Although not
required, JEDEC specications recommend when a LOAD
MODE REGISTER command is issued to reset the DLL, it
should always be followed by a LOAD MODE REGISTER
command to select normal operating mode.
All other combinations of values for A7-A12 are reserved
for future use and/or test modes. Test modes and reserved
states should not be used because unknown operation or
incompatibility with future versions may result.
EXTENDED MODE REGISTER
The extended mode register controls functions beyond
those controlled by the mode register; these additional
functions are DLL enable/disable, output drive strength,
and QFC. These functions are controlled via the bits shown
in Figure 5. The extended mode register is programmed
via the LOAD MODE REGISTER command to the mode
register (with BA0 = 1 and BA1 = 0) and will retain the
stored information until it is programmed again or the
White Electronic Designs Corp. reserves the right to change products or specications without notice.
July 2006
Rev. 6
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

5 Page





W3E32M72S-XSBX arduino
White Electronic Designs
W3E32M72S-XSBX
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1-5, 16)
VCC, VCCQ = +2.5V ± 0.2V; -55°C TA +125°C
Parameter/Condition
Supply Voltage (36, 41)
I/O Supply Voltage (36, 41, 44)
Input Leakage Current: Any input 0V VIN VCC (All other pins not under test = 0V)
Input Leakage Address Current (All other pins not under test = 0V)
Output Leakage Current: I/Os are disabled; 0V VOUT VCCQ
Output Levels: Full drive option (37, 39)
High Current (VOUT = VCCQ - 0.373V, minimum VREF, minimum VTT)
Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)
Output Levels: Reduced drive option (38, 39)
High Current (VOUT = VCCQ - 0.763V, minimum VREF, minimum VTT)
Low Current (VOUT = 0.763V, maximum VREF, maximum VTT)
I/O Reference Voltage (6,44)
I/O Termination Voltage (7, 44)
Symbol
VCC
VCCQ
II
II
IOZ
IOH
IOL
IOHR
IOLR
VREF
VTT
Min
2.3
2.3
-2
-10
-5
-16.8
16.8
-9
9
0.49 x VCCQ
VREF - 0.04
Max
2.7
2.7
2
10
5
-
-
-
-
0.51 x VCCQ
VREF + 0.04
Units
V
V
µA
µA
µA
mA
mA
mA
mA
V
V
Parameter/Condition
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
AC INPUT OPERATING CONDITIONS
VCC, VCCQ = +2.5V ± 0.2V; -55°C TA +125°C
Symbol
VIH
VIL
Min
VREF +0.500
Max
VREF -0.500
Units
V
V
White Electronic Designs Corp. reserves the right to change products or specications without notice.
July 2006
Rev. 6
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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