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Número de pieza W3E16M64S-XBX
Descripción 16Mx64 DDR SDRAM
Fabricantes White Electronic 
Logotipo White Electronic Logotipo



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White Electronic Designs
W3E16M64S-XBX
16Mx64 DDR SDRAM
FEATURES
DDR Data Rate = 200, 250, 266Mbps
Package:
• 219 Plastic Ball Grid Array (PBGA), 21 x 25mm
2.5V ±0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Differential clock inputs (CLK and CLK#)
Commands entered on each positive CLK edge
Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (one per byte)
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
DLL to align DQ and DQS transitions with CLK
Four internal banks for concurrent operation
www.DataSheet4U.com
Two data mask (DM) pins for masking write data
Programmable IOL/IOH option
Auto precharge option
Auto Refresh and Self Refresh Modes
Commercial, Industrial and Military Temperature
Ranges
Organized as 16M x 64
Weight: W3E16M64S-XBX - 2 grams typical
* This product is subject to change without notice.
BENEFITS
50% SPACE SAVINGS
Reduced part count
Reduced I/O count
• 17% I/O Reduction
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
Upgradeable to 32M x 64 density
(W3E32M64S-XBX)
GENERAL DESCRIPTION
The 128MByte (1Gb) DDR SDRAM is a high-speed CMOS,
dynamic random-access, memory using 4 chips containing
268,435,456 bits. Each chip is internally configured as a
quad-bank DRAM. Each of the chip’s 67,108,864-bit banks
is organized as 8,192 rows by 512 columns by 16 bits.
The 128 MB DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 128MB DDR SDRAM effectively consists
of a single 2n-bit wide, one-clock-cycle data tansfer at the
internal DRAM core and two corresponding n-bit wide,
one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during READs
February 2005
Rev. 4
Monolithic Solution
11.9 11.9 11.9 11.9
22.3
66
TSOP
TS6O6 PTS6O6 PTS6O6 P TS6O6TPS6O6 P
TST6OS66O6PP
Area
I/O
Count
4 x 265mm2 = 1060mm2
4 x 66 pins = 264 pins
Actual Size
W3E16M64S-XBX
21
White Electronic Designs
W3E16M64S-XBX
25
525mm2
S
A
V
I
N
G
S
50%
219 Balls
17%
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 page




W3E16M64S-XBX pdf
White Electronic Designs
W3E16M64S-XBX
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to define the specific mode of
operation of the DDR SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency,
and an operating mode, as shown in Figure 3. The Mode
Register is programmed via the MODE REGISTER SET
command (with BA0 = 0 and BA1 = 0) and will retain
the stored information until it is programmed again or
the device loses power. (Except for bit A8 which is self
clearing).
Reprogramming the mode register will not alter the contents
of the memory, provided it is performed correctly. The Mode
Register must be loaded (reloaded) when all banks are
idle and no bursts are in progress, and the controller must
wait the specified time before initiating the subsequent
operation. Violating either of these requirements will result
in unspecified operation.
Mode register bits A0-A2 specify the burst length, A3
specifies the type of burst (sequential or interleaved),
A4-A6 specify the CAS latency, and A7-A12 specify the
operating mode.
BURST LENGTH
Read and write accesses to the DDR SDRAM are burst
oriented, with the burst length being programmable,
as shown in Figure 3. The burst length determines
the maximum number of column locations that can be
accessed for a given READ or WRITE command. Burst
lengths of 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning
that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-Ai when the
burst length is set to two; by A2-Ai when the burst length
is set to four (where Ai is the most significant column
address for a given configuration); and by A3-Ai when the
burst length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting location
within the block. The programmed burst length applies to
both READ and WRITE bursts.
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
READ LATENCY
The READ latency is the delay, in clock cycles, between
the registration of a READ command and the availability
of the first bit of output data. The latency can be set to 2
or 2.5 clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n+m. Table 2 below indicates the operating frequencies at
which each CAS latency setting can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
TABLE 2 – CAS LATENCY
SPEED
-200
-250
-266
ALLOWABLE OPERATING
FREQUENCY (MHz)
CAS
LATENCY = 2
75
100
100
CAS
LATENCY = 2.5
100
125
133
OPERATING MODE
The normal operating mode is selected by issuing a MODE
REGISTER SET command with bits A7-A12 each set to
zero, and bits A0-A6 set to the desired values. A DLL reset
is initiated by issuing a MODE REGISTER SET command
with bits A7 and A9-A12 each set to zero, bit A8 set to one,
and bits A0-A6 set to the desired values. Although not
required, JEDEC specifications recommend when a LOAD
MODE REGISTER command is issued to reset the DLL, it
should always be followed by a LOAD MODE REGISTER
command to select normal operating mode.
All other combinations of values for A7-A12 are reserved
for future use and/or test modes. Test modes and reserved
states should not be used because unknown operation or
incompatibility with future versions may result.
February 2005
Rev. 4
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

5 Page





W3E16M64S-XBX arduino
White Electronic Designs
W3E16M64S-XBX
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1, 6)
VCC = +2.5V ±0.2V; -55°C ≤ TA ≤ +125°C
Parameter/Condition
Symbol
Min
Max
Supply Voltage
I/O Supply Voltage
Input High Voltage: Logic 1; All inputs (21)
Input Low Voltage: Logic 0; All inputs (21)
Input Leakage Current: Any input 0V ≤ VIN ≤ VCC (All other pins not under test = 0V)
Input Leakage Address Current (All other pins not under test = 0V)
Output Leakage Current: I/Os are disabled; 0V ≤ VOUT ≤ VCC
Output Levels: Full drive option
High Current (VOUT = VCCQ - 0.373V, minimum VREF, minimum VTT)
Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)
Output Levels: Reduced drive option
High Current (VOUT = VCCQ - 0.763V, minimum VREF, minimum VTT)
Low Current (VOUT = 0.763V, maximum VREF, maximum VTT)
I/O Reference Voltage
I/O Termination Voltage
VCC
VCCQ
VIH
VIL
II
II
IOZ
IOH
IOL
IOHR
IOLR
VREF
VTT
2.3
2.3
VREF - 0.04
-0.3
-2
-8
-5
-12
12
2.7
2.7
VREF + 0.04
VREF - 0.15
2
8
5
-9 —
9—
0.49 x VCCQ
VREF - 0.04
0.51 x VCCQ
VREF + 0.04
Units
V
V
V
V
µA
µA
µA
mA
mA
mA
mA
V
V
ICC SPECIFICATIONS AND CONDITIONS (NOTES 1-5, 10, 12, 14)
VCC = +2.5V ±0.2V; -55°C ≤ TA ≤ +125°C
Max
Parameter/Condition
OPERATING CURRENT: One bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs
changing once per clock cyle; Address and control inputs changing once every two clock cycles; (22, 48)
OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA;
Address and control inputs changing once per clock cycle (22, 48)
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK (MIN); CKE =
LOW; (23, 32, 50)
IDLE STANDBY CURRENT: CS = HIGH; All banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control
inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM (51)
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW
(23, 32, 50)
ACTIVE STANDBY CURRENT: CS = HIGH; CKE = HIGH; One bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK
(MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once
per clock cycle (22)
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA (22, 48)
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle (22)
AUTO REFRESH CURRENT
tRC = tRC (MIN) (27, 50)
tRC = 7.8125µs (27, 50)
SELF REFRESH CURRENT: CKE ≤ 0.2V
Standard (11)
OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge, tRC =tRC (MIN); tCK = tCK
(MIN); Address and control inputs change only during Active READ or WRITE commands. (22, 49)
250Mbps
Symbol 266Mbps 200Mbps
ICC0 500 480
ICC1 680 620
ICC2P
16
16
ICC2F
180
180
ICC3P
120
120
ICC3N
200
200
ICC4R
740
740
ICC4W
640
640
ICC5
ICC5A
ICC6
ICC7
980
24
16
1600
980
24
16
1600
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
February 2005
Rev. 4
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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