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PDF W3E16M72S-XBX Data sheet ( Hoja de datos )
| Número de pieza | W3E16M72S-XBX | |
| Descripción | 16Mx72 Registered DDR SDRAM | |
| Fabricantes | White Electronic | |
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White Electronic Designs
W3E16M72SR-XBX
16Mx72 Registered DDR SDRAM
FEATURES
Registered for enhanced performance of bus
speeds of 200, 225, and 250 MHz
Package:
Auto Refresh and Self Refresh Modes
Commercial, Industrial and Military Temperature
Ranges
• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm
Organized as 16M x 72
2.5V ±0.2V core power supply
Weight: W3E16M72SR-XBX - 2.5 grams typical
2.5V I/O (SSTL_2 compatible)
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (one per byte)
DQS edge-aligned with data for READs; center-
www.DataSheet4U.caomligned with data for WRITEs
DLL to align DQ and DQS transitions with CK
BENEFITS
47% SPACE SAVINGS
Glueless Connection to PCI Bridge/Memory
Controller
Reduced part count
Reduced I/O count
• 49% I/O Reduction
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
Four internal banks for concurrent operation
Two data mask (DM) pins for masking write data
Upgradeable to 32M x 72 density (contact factory
for information)
Programmable IOL/IOH option
Auto precharge option
* This product is subject to change without notice.
Monolithic Solution
22.3
66
11.9 TSOP
11.9 11.9
22.3
66
TSOP
11.9
8.3
12.6
48
TSOP
66
22.3 TSOP
66
TSOP
66
TSOP
12.6
48
TSOP
Actual Size
S
A
V
White Electronic Designs 25 I
W3E16M72SR-XBX
N
G
32 S
Area
I/O
Count
February 2005
Rev. 2
5 x 265mm2 + 2 x 105mm2 = 1536mm2
5 x 66 pins + 2 x 48 = 426 pins
800mm2
219 Balls
47%
49%
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
W3E16M72SR-XBX
Once the 200µs delay has been satisfied, a DESELECT
or NOP command should be applied, and CKE should
be brought HIGH. Following the NOP command, a
PRECHARGE ALL command should be applied. Next a
LOAD MODE REGISTER command should be issued for
the extended mode register (BA1 LOW and BA0 HIGH)
to enable the DLL, followed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1
both LOW) to reset the DLL and to program the operating
parameters. Two-hundred clock cycles are required
between the DLL reset and any READ command. A
PRECHARGE ALL command should then be applied,
placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must
be performed (tRFC must be satisfied.) Additionally, a LOAD
MODE REGISTER command for the mode register with
the reset DLL bit deactivated (i.e., to program operating
parameters without resetting the DLL) is required.
Following these requirements, the DDR SDRAM is ready
for normal operation.
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to define the specific mode of
operation of the DDR SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency,
and an operating mode, as shown in Figure 3. The Mode
Register is programmed via the MODE REGISTER SET
command (with BA0 = 0 and BA1 = 0) and will retain
the stored information until it is programmed again or
the device loses power. (Except for bit A8 which is self
clearing).
Reprogramming the mode register will not alter the contents
of the memory, provided it is performed correctly. The
Mode Register must be loaded (reloaded) when all banks
are idle and no bursts are in progress, and the controller
must wait the specified time before initiating the subsequent
operation. Violating either of these requirements will result
in unspecified operation.
Mode register bits A0-A2 specify the burst length, A3
specifies the type of burst (sequential or interleaved),
A4-A6 specify the CAS latency, and A7-A12 specify the
operating mode.
BURST LENGTH
Read and write accesses to the DDR SDRAM are burst
oriented, with the burst length being programmable,
as shown in Figure 3. The burst length determines
the maximum number of column locations that can be
accessed for a given READ or WRITE command. Burst
lengths of 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning
that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-Ai when the
burst length is set to two; by A2-Ai when the burst length
is set to four (where Ai is the most significant column
address for a given configuration); and by A3-Ai when the
burst length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting location
within the block. The programmed burst length applies to
both READ and WRITE bursts.
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
READ LATENCY
The READ latency is the delay, in clock cycles, between
the registration of a READ command and the availability
of the first bit of output data. The latency can be set to 2
or 2.5 clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n+m. Table 2 below indicates the operating frequencies at
which each CAS latency setting can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
February 2005
Rev. 2
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page 
White Electronic Designs
W3E16M72SR-XBX
DDR DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1, 6)
VCC = +2.5V ± 0.2V; -55°C ≤ TA ≤ +125°C
Parameter/Condition
Supply Voltage
I/O Supply Voltage
Input Hight Voltage: Logic 1; All inputs (21)
Input Low Voltage: Logic 0; All inputs (21)
Input Leakage Current: Any input 0V ≤ VIN ≤ VCC (All other pins not under test = 0V)
Output Leakage Current: I/Os are disabled; 0V ≤ VOUT ≤ VCC
Output Levels: Full drive option - x16
High Current (VOUT = VCCQ - 0.373V, minimum VREF, minimum VTT)
Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)
Output Levels: Reduced drive option - 16 only
High Current (VOUT = VCCQ - 0.763V, minimum VREF, minimum VTT)
Low Current (VOUT = 0.763V, maximum VREF, maximum VTT)
I/O Reference Voltage
I/O Termination Voltage
Symbol
VCC
VCCQ
VIH
VIL
II
IOZ
IOH
IOL
IOHR
IOLR
VREF
VTT
Min
2.3
2.3
VREF + 0.15
-0.4
-2
-5
-16.8
16.8
-9
9
0.49 x VCCQ
VREF - 0.04
Max
2.7
2.7
VCC + 0.3
VREF - 0.15
2
5
–
–
–
–
0.51 x VCCQ
VREF + 0.04
Units
V
V
V
V
µA
µA
mA
mA
mA
mA
V
V
DDR ICC SPECIFICATIONS AND CONDITIONS (NOTES 1-5, 10, 12, 14, 54)
VCC = +2.5V ± 0.2V; -55°C ≤ TA ≤ +125°C
Parameter/Condition
OPERATING CURRENT: One bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once
per clock cyle; Address and control inputs changing once every two clock cycles; (22, 48)
OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and
control inputs changing once per clock cycle (22, 48)
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW; (23, 32, 50)
IDLE STANDBY CURRENT: CS# = HIGH; All banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing
once per clock cycle. VIN = VREF for DQ, DQS, and DM (51)
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW (23, 32, 50)
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ,
DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle (22)
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); IOUT = 0mA (22, 48)
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle (22)
AUTO REFRESH CURRENT
tREF = tRC (MIN) (27, 50)
tREF = 7.8125µs (27, 50)
SELF REFRESH CURRENT: CKE ≤ 0.2V
Standard (11)
OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge, tRC =tRC (MIN); tCK = tCK (MIN); Address and
control inputs change only during Active READ or WRITE commands. (22, 49)
Max
250Mbps
Symbol 266Mbps 200Mbps
ICC0 625 600
ICC1 850 775
ICC2P
20
20
ICC2F 225 225
ICC3P 150 150
ICC3N 250 250
ICC4R 925 925
ICC4W
800
800
ICC5 1225 1225
ICC5A
30
30
ICC6 20
20
ICC7 2000 2000
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
February 2005
Rev. 2
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet W3E16M72S-XBX.PDF ] | |
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