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PDF X98014 Data sheet ( Hoja de datos )
| Número de pieza | X98014 | |
| Descripción | 140MHz Triple Video Digitizer | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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NTOHTERISELC9OI8MM0P0M1RE-O1N4VD0EEIDSDAAFLO1T®R0E0RN%NECAWOTDDIMVaEEPtSaAIGTSINhBSeLeE-t
140MHz Triple Video Digitizer with
Digital PLL
The X98014 3-channel, 8-bit Analog Front End (AFE)
contains all the components necessary to digitize analog
RGB or YUV graphics signals from personal computers,
workstations and video set-top boxes. The fully differential
analog design provides high PSRR and dynamic
performance to meet the stringent requirements of the
graphics display industry. The AFE’s 140MSPS conversion
rate supports resolutions up to SXGA at 75Hz refresh rate,
while the front end's high input bandwidth ensures sharp
images at the highest resolutions.
To minimize noise, the X98014's analog section features 2
sets of pseudo-differential RGB inputs with programmable
input bandwidth, as well as internal DC restore clamping
(including mid-scale clamping for YUV signals). This is
followed by the programmable gain/offset stage and the
three 140MSPS Analog-to-Digital Converters (ADCs).
Automatic Black Level Compensation (ABLC™) eliminates
part-to-part offset variation, ensuring perfect black level
performance in every application.
The X98014's digital PLL generates a pixel clock from the
analogwww.DataSheet4U.com source's HSYNC or SOG (Sync-On-Green) signals.
Pixel clock output frequencies range from 10MHz to 140MHz
with sampling clock jitter of 250ps peak to peak.
Simplified Block Diagram
March 8, 2006
X98014
FN8217.3
Features
• 140MSPS maximum conversion rate
• Low PLL clock jitter (250ps p-p @ 140MSPS)
• 64 interpixel sampling positions
• 0.35Vp-p to 1.4Vp-p video input range
• Programmable bandwidth (100MHz to 780MHz)
• 2 channel input multiplexer
• RGB and YUV 4:2:2 output formats
• 5 embedded voltage regulators allow operation from
single 3.3V supply and enhance performance, isolation
• Completely independent 8 bit gain/10 bit offset control
• CSYNC and SOG support
• Trilevel sync detection
• 990mW typical PD @ 140MSPS
• Pb-free plus anneal available (RoHS compliant)
Applications
• LCD Monitors and Projectors
• Digital TVs
• Plasma Display Panels
• RGB Graphics Processing
• Scan Converters
RGB/YPbPrIN 1
RGB/YPbPrIN 2
3
3
Voltage
Clamp
PGA
Offset
DAC
ABLC™
+ 8 bit ADC
SOGIN1/2
HSYNCIN1/2
VSYNCIN1/2
Sync
Processing
Digital PLL
AFE Configuration and Control
8 or 16
RGB/YUVOUT
x3
HSYNCOUT
VSYNCOUT
HSOUT
PIXELCLKOUT
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
X98014
Electrical Specifications Specifications apply for VA = VD = VX = 3.3V, pixel rate = 140MHz, fXTAL = 25MHz, TA = 25°C,
unless otherwise noted (Continued)
SYMBOL
PARAMETER
COMMENT
MIN TYP MAX
tSETUP DATA valid before rising edge of DATACLK 15pF DATACLK load, 15pF DATA load
(Note 1)
1.3
tHOLD DATA valid after rising edge of DATACLK 15pF DATACLK load, 15pF DATA load
(Note 1)
2.0
AC TIMING CHARACTERISTICS (2 WIRE INTERFACE)
fSCL
SCL Clock Frequency
Maximum width of a glitch on SCL that will 2 XTAL periods min
be suppressed
0 400
80
tAA SCL LOW to SDA Data Out Valid
5 XTAL periods plus SDA’s RC time
constant
See
comment
tBUF
Time the bus must be free before a new
transmission can start
1.3
tLOW Clock LOW Time
tHIGH Clock HIGH Time
tSU:STA Start Condition Setup Time
tHD:STA Start Condition Hold Time
tSU:DAT Data In Setup Time
tHD:DAT Data In Hold Time
tSU:STO Stop Condition Setup Time
tDH Data Output Hold Time
4 XTAL periods min
NOTES:
1. Setup and hold times are at a 140MHz DATACLK rate.
1.3
0.6
0.6
0.6
100
0
0.6
160
UNIT
ns
ns
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
SCL
SDA IN
tSU:ST
SDA OUT
tF tHIGH
tSU:DAT
tHD:STA
tLOW
tHD:DAT
tR
tAA tDH
FIGURE 1. 2 WIRE INTERFACE TIMING
tSU:STO
tBUF
DATACLK
DATACLK
Pixel Data
tSETUP
tHOLD
FIGURE 2. DATA OUTPUT SETUP AND HOLD TIMING
5
FN8217.3
March 8, 2006
5 Page 
X98014
Register Listing
ADDRESS REGISTER (DEFAULT VALUE)
0x01
SYNC Status
(read only)
0x02
SYNC Polarity
(read only)
0x03
HSYNC Slicer (0x44)
0x04
SOG Slicer (0x08)
BIT(s) FUNCTION NAME
0 HSYNC1 Active
1 HSYNC2 Active
2 VSYNC1 Active
3 VSYNC2 Active
4 SOG1 Active
5 SOG2 Active
6 PLL Locked
7 CSYNC Detected at
Sync Splitter Output
0 HSYNC1
Polarity
1 HSYNC2
Polarity
2 VSYNC1
Polarity
3 VSYNC2
Polarity
4 HSYNC1
Trilevel
5 HSYNC2
Trilevel
7:6 N/A
2:0 HSYNC1 Threshold
3 Reserved
6:4 HSYNC2 Threshold
7 Disable Glitch Filter
3:0 SOG1 and SOG2
Threshold
4 SOG Filter
Enable
5 SOG Hysteresis
Disable
7:6 Reserved
DESCRIPTION
0: HSYNC1 is Inactive
1: HSYNC1 is Active
0: HSYNC2 is Inactive
1: HSYNC2 is Active
0: VSYNC1 is Inactive
1: VSYNC1 is Active
0: VSYNC2 is Inactive
1: VSYNC2 is Active
0: SOG1 is Inactive
1: SOG1 is Active
0: SOG2 is Inactive
1: SOG2 is Active
0: PLL is unlocked
1: PLL is locked to incoming HSYNC
0: Composite Sync signal not detected
1: Composite Sync signal is detected
0: HSYNC1 is Active High
1: HSYNC1 is Active Low
0: HSYNC2 is Active High
1: HSYNC2 is Active Low
0: VSYNC1 is Active High
1: VSYNC1 is Active Low
0: VSYNC2 is Active High
1: VSYNC2 is Active Low
0: HSYNC1 is Standard Sync
1: HSYNC1 is Trilevel Sync
0: HSYNC2 is Standard Sync
1: HSYNC2 is Trilevel Sync
Returns 0
000 = lowest (0.4V) All values referred to
100 = default (2.0V) voltage at HSYNC input
111 = highest (3.2V) pin, 240mV hysteresis
Set to 00
See HSYNC1
0: HSYNC/VSYNC Digital Glitch Filter Enabled (default)
1: HSYNC/VSYNC Digital Glitch Filter Disabled
0x0 = lowest (0mV) 40mV hysteresis at
0x8 = default (160mV) all settings
0xF = highest (300mV) 20mV step size
0: SOG low pass filter disabled (default)
1: SOG low pass filter enabled, 14MHz corner
0: 40mV SOG hysteresis enabled
1: 40mV SOG hysteresis disabled (default)
Set to 00.
11 FN8217.3
March 8, 2006
11 Page | ||
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| PDF Descargar | [ Datasheet X98014.PDF ] | |
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