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PDF X95840 Data sheet ( Hoja de datos )
| Número de pieza | X95840 | |
| Descripción | Quad Digital Controlled Potentiometers | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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X95840
®
Quad Digital Controlled Potentiometers (XDCP™)
Data Sheet
July 5, 2006
FN8213.2
Low Noise/Low Power/I2C® Bus/256 Taps
The X95840 integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS integrated
circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. Each potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR), that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power up the device recalls the contents of the four
DCP’s IVR to the corresponding WRs.
The DCPs can be used as three-terminal potentiometers or
as two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Ordering Information
PART NUMBER
PART
RESISTANCE
MARKING
OPTION
PACKAGE
www.DataSheet4U.comX95840WV20I-2.7* X95840WV G
X95840WV20IZ-2.7* X95840WV Z G
(Note)
10kΩ
10kΩ
20 Ld TSSOP
20 Ld TSSOP
(Pb-free)
X95840UV20I-2.7* X95840UV G
50kΩ 20 Ld TSSOP
X95840UV20IZ-2.7* X95840UV Z G
(Note)
50kΩ
20 Ld TSSOP
(Pb-free)
*Add “T1” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Features
• Four Potentiometers in One Package
• 256 Resistor Taps-0.4% Resolution
• I2C Serial Interface
- Three address pins, up to eight devices/bus
• Wiper Resistance: 70Ω Typical @ 3.3V
• Non-Volatile Storage of Wiper Position
• Standby Current < 5µA Max
• Power Supply: 2.7V to 5.5V
• 50kΩ, 10kΩ Total Resistance
• High Reliability
- Endurance: 150,000 data changes per bit per register
- Register data retention: 50 years @ T ≤ 75°C
• 20 Ld TSSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
Pinouts
X95840
(20 LD TSSOP)
TOP VIEW
RH3
RL3
RW3
A2
SCL
SDA
GND
RW2
RL2
RH2
1
2
3
4
5
6
7
8
9
10
20 RW0
19 RL0
18 RH0
17 WP
16 VCC
15 A1
14 A0
13 RH1
12 RL1
11 RW1
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
X95840
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (Note 1)
tSU:DAT Input Data Setup Time
From SDA exiting the 30% to 70% of VCC window, to
SCL rising edge crossing 30% of VCC
tHD:DAT Input Data Hold Time
From SCL rising edge crossing 70% of VCC to SDA
entering the 30% to 70% of VCC window.
tSU:STO
STOP Condition Setup Time From SCL rising edge crossing 70% of VCC, to SDA
rising edge crossing 30% of VCC.
tHD:STO
STOP Condition Setup Time From SDA rising edge to SCL falling edge. Both
crossing 70% of VCC.
tDH (Note 15) Output Data Hold Time
From SCL falling edge crossing 30% of VCC, until SDA
enters the 30% to 70% of VCC window.
tR (Note 15) SDA and SCL Rise Time
From 30% to 70% of VCC
100
0
600
600
0
20 +
0.1 * Cb
tF (Note 15) SDA and SCL Fall Time
From 70% to 30% of VCC
20 +
0.1 * Cb
Cb (Note 15) Capacitive Loading of SDA Total on-chip and off-chip
or SCL
10
Rpu (Note 15) SDA and SCL Bus Pull-up
Resistor Off-chip
Maximum is determined by tR and tF.
For Cb = 400pF, max is about 2~2.5kΩ.
For Cb = 40pF, max is about 15~20kΩ
1
tWP Non-volatile Write Cycle
(Notes 15, 16) Time
12
tSU:WPA
A2, A1, A0, and WP Setup Before START condition
Time
600
tHD:WPA
A2, A1, A0, and WP Hold
Time
After STOP condition
600
MAX
250
250
400
20
SDA vs SCL Timing
tF
tHIGH
tLOW
tR
UNITS
ns
ns
ns
ns
ns
ns
ns
pF
kΩ
ms
ns
ns
SCL
tSU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
tSU:DAT
tHD:STA
tHD:DAT
tAA tDH
tSU:STO
tBUF
5 FN8213.2
July 5, 2006
5 Page 
X95840
SCL from Master
SDA Output from
Transmitter
1
89
High Impedance
SDA Output from
Receiver
High Impedance
START
FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER
ACK
Signals from the
Master
Write
S
t
a Identification
r Byte
t
Address
Byte
Data
Byte
Signal at SDA
Signals from the
X95840
1 0 1 0 A2A1A00 0 0 0 0
A
C
K
A
C
K
S
t
o
p
A
C
K
FIGURE 17. BYTE WRITE SEQUENCE
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
X95840 responds with an ACK. At this time, if the Data Byte
is to be written only to volatile registers, then the device
enters its standby state. If the Data Byte is to be written also
to non-volatile memory, the X95840 begins its internal write
cycle to non-volatile memory. During the internal non-volatile
write cycle, the device ignores transitions at the SDA and
SCL pins, and the SDA output is at a high impedance state.
When the internal non-volatile write cycle is completed, the
X95840 enters its standby state (See Figure 17).
The byte at address 00001000 bin (8 decimal) determines if
the Data Byte is to be written to volatile and/or non-volatile
memory. See “Memory Description” on page 9.
Data Protection
The WP pin has to be at logic HIGH to perform any Write
operation to the device. When the WP is active (LOW) the
device ignores Data Bytes of a Write Operation, does not
respond to the Data Bytes with an ACK, and instead, goes to
its standby state waiting for a new START condition.
A STOP condition also acts as a protection of non-volatile
memory. A valid Identification Byte, Address Byte, and total
number of SCL pulses act as a protection of both volatile
and non-volatile registers. During a Write sequence, the
Data Byte is loaded into an internal shift register as it is
received. If the Address Byte is 0, 1, 2, 3, or 8 decimal, the
Data Byte is transferred to the appropriate Wiper Register
(WR) or to the Access Control Register, at the falling edge of
the SCL pulse that loads the last bit (LSB) of the Data Byte.
If the Address Byte is between 0 and 6 (inclusive), and the
Access Control Register is all zeros (default), then the STOP
condition initiates the internal write cycle to non-volatile
memory.
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 18). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the X95840 responds with an ACK. Then the X95840
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eight bit of each
byte. The master terminates the read operation (issuing a
11 FN8213.2
July 5, 2006
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet X95840.PDF ] | |
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