DataSheet.es    


PDF X9520 Data sheet ( Hoja de datos )

Número de pieza X9520
Descripción Dual Voltage Monitors
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



Hay una vista previa y un enlace de descarga de X9520 (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! X9520 Hoja de datos, Descripción, Manual

®
PRELIMINARY
X9520
Fiber Channel/Gigabit Ethernet Laser Diode Control for Fiber Optic Modules
Data Sheet
January 3, 2006
FN8206.1
Triple DCP, POR, 2kbit EEPROM Memory,
Dual Voltage Monitors
The X9520 combines three Digitally Controlled
Potentiometers (DCPs), V1/Vcc Power-on Reset (POR)
circuitry, two programmable voltage monitor inputs with
software and hardware indicators, and integrated EEPROM
with Block Lock™ protection. All functions of the X9520 are
accessed by an industry standard 2-Wire serial interface.
Two of the DCPs of the X9520 may be utilized to control the
bias and modulation currents of the laser diode in a Fiber Optic
module. The third DCP may be used to set other various
reference quantities, or as a coarse trim for one of the other two
DCPs. The 2kbit integrated EEPROM may be used to store
module definition data. The programmable POR circuit may be
used to ensure that V1/Vcc is stable before power is applied to
the laser diode/module. The programmable voltage monitors
may be used for monitoring various module alarm levels.
The features of the X9520 are ideally suited to simplifying the
design of fiber optic modules which comply to the Gigabit
Interface Converter (GBIC) specification. The integration of
these functions into one package significantly reduces board
area, cost and increases reliability of laser diode modules.
www.DataSheet4U.com
Ordering Information
PART
TEMP.
PART NUMBER MARKING RANGE (°C)
PACKAGE
X9520B20I-A
-40 to +85 20 Ld CSP
X9520B20I-AT1
-40 to +85 20 Ld CSP
X9520B20I-BT1
-40 to +85 20 Ld CSP
X9520V20I-A
X9520V IA -40 to +85 20 Ld TSSOP
X9520V20I-AT1 X9520V IA -40 to +85 20 Ld TSSOP
X9520V20I-B
X9520V IB -40 to +85 20 Ld TSSOP
X9520V20I-BT1 X9520V IB -40 to +85 20 Ld TSSOP
X9520V20IZ-A
X9520V ZIA -40 to +85 20 Ld TSSOP
(Pb-free)
X9520V20IZ-AT1 X9520V ZIA -40 to +85 20 Ld TSSOP
(Pb-free)
X9520V20IZ-B
X9520V ZIB -40 to +85 20 Ld TSSOP
(Pb-free)
X9520V20IZ-BT1 X9520V ZIB -40 to +85 20 Ld TSSOP
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Features
• Three Digitally Controlled Potentiometers (DCPs)
- 64 Tap - 10k
- 100 Tap - 10k
- 256 Tap - 100k
- Nonvolatile
- Write Protect Function
• 2kbit EEPROM Memory with Write Protect & Block Lock
• 2-Wire Industry Standard Serial Interface
- Complies to the Gigabit Interface Converter (GBIC)
specification
• Power-on Reset (POR) Circuitry
- Programmable Threshold Voltage
- Software Selectable Reset Timeout
- Manual Reset
• Two Supplementary Voltage Monitors
- Programmable Threshold Voltages
• Single Supply Operation
- 2.7V to 5.5V
• Hot Pluggable
• 20 Ld Packages
- CSP (Chip Scale Package)
- TSSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
©2000 Intersil Inc., Patents Pending. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 page




X9520 pdf
SCSLCfrLom
Mfraosmter
Master
Data Output from
Transmitter
X9520
18
9
Data Output from
Receiver
Start
Acknowledge
FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER
SERIAL ACKNOWLEDGE
An ACKNOWLEDGE (ACK) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will pull the
SDA line LOW to ACKNOWLEDGE that it received the eight
bits of data. Refer to Figure 3.
The device will respond with an ACKNOWLEDGE after
recognition of a START condition if the correct Device
Identifier bits are contained in the Slave Address Byte. If a
write operation is selected, the device will respond with an
ACKNOWLEDGE after the receipt of each subsequent eight
bit word.
In the read mode, the device will transmit eight bits of data,
release the SDA line, then monitor the line for an
ACKNOWLEDGE. If an ACKNOWLEDGE is detected and
no STOP condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an ACKNOWLEDGE is not
detected. The master must then issue a STOP condition to
place the device into a known state.
Device Internal Addressing
Addressing Protocol Overview
The user addressable internal components of the X9520 can
be split up into three main parts:
• Three Digitally Controlled Potentiometers (DCPs)
• EEPROM array
• Control and Status (CONSTAT) Register
Depending upon the operation to be performed on each of
these individual parts, a 1, 2 or 3 Byte protocol is used. All
operations however must begin with the Slave Address Byte
being issued on the SDA pin. The Slave address selects the
part of the X9520 to be addressed, and specifies if a Read or
Write operation is to be performed.
It should be noted that in order to perform a write operation
to either a DCP or the EEPROM array, the Write Enable
Latch (WEL) bit must first be set (See “BL1, BL0: Block Lock
protection bits - (Nonvolatile)” on page 13.)
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4.). This byte consists
of three parts:
• The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4). The
Device Type Identifier must always be set to 1010 in order
to select the X9520.
• The next three bits (SA3 - SA1) are the Internal Device
Address bits. Setting these bits to 000 internally selects
the EEPROM array, while setting these bits to 111 selects
the DCP structures in the X9520. The CONSTAT Register
may be selected using the Internal Device Address 010.
• The Least Significant Bit of the Slave Address (SA0) Byte
is the R/W bit. This bit defines the operation to be
performed on the device being addressed (as defined in
the bits SA3 - SA1). When the R/W bit is “1”, then a READ
operation is selected. A “0” selects a WRITE operation
(Refer to Figure 4.)
5 FN8206.1
January 3, 2006

5 Page





X9520 arduino
X9520
7 bytes
5 byte5sbytes
address
= 6 10
address
1110
address
15 10
address pointer
ends here
Addr = 7 10
FIGURE 13. EXAMPLE: WRITING 12 BYTES TO A 16-BYTE PAGE STARTING AT LOCATION 11.
Signals from the
Master
SDA Bus
Signals from the
Slave
S
t
a
r
Slave
t Address
1 0 1 0 0 0 01
A
C
K
Data
S
t
o
p
FIGURE 14. CURRENT EEPROM ADDRESS READ SEQUENCE
EEPROM Array Read Operations
Read operations are initiated in the same manner as write
operations with the exception that the R/W bit of the Slave
Address Byte is set to one. There are three basic read
operations: Current EEPROM Address Read, Random
EEPROM Read, and Sequential EEPROM Read.
Current EEPROM Address Read
Internally the device contains an address counter that
maintains the address of the last word read incremented by
one. Therefore, if the last read was to address n, the next
read operation would access data from address n+1. On
power-up, the address of the address counter is undefined,
requiring a read or write operation for initialization.
Upon receipt of the Slave Address Byte with the R/W bit set
to one, the device issues an ACKNOWLEDGE and then
transmits the eight bits of the Data Byte. The master
terminates the read operation when it does not respond with
an ACKNOWLEDGE during the ninth clock and then issues
a STOP condition (See Figure 14 for the address,
ACKNOWLEDGE, and data transfer sequence).
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read operation,
the master must either issue a STOP condition during the
ninth cycle or hold SDA HIGH during the ninth clock cycle
and then issue a STOP condition.
Another important point to note regarding the “Current
EEPROM Address Read” , is that this operation is not
available if the last executed operation was an access to a
DCP or the CONSTAT Register (i.e.: an operation using the
Device Type Identifier 1010111 or 1010010). Immediately
after an operation to a DCP or CONSTAT Register is
performed, only a “Random EEPROM Read” is available.
Immediately following a “Random EEPROM Read” , a
“Current EEPROM Address Read” or “Sequential EEPROM
Read” is once again available (assuming that no access to a
DCP or CONSTAT Register occur in the interim).
Random EEPROM Read
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master must
first perform a “dummy” write operation. The master issues
the START condition and the Slave Address Byte, receives
an ACKNOWLEDGE, then issues an Address Byte. This
“dummy” Write operation sets the address pointer to the
address from which to begin the random EEPROM read
operation.
After the X9520 acknowledges the receipt of the Address
Byte, the master immediately issues another START
condition and the Slave Address Byte with the R/W bit set to
one. This is followed by an ACKNOWLEDGE from the
X9520 and then by the eight bit word. The master terminates
11 FN8206.1
January 3, 2006

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet X9520.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
X9520Dual Voltage MonitorsIntersil Corporation
Intersil Corporation
X9521Dual DCP/ EEPROM MemoryXicor
Xicor
X9521EEPROM MemoryIntersil Corporation
Intersil Corporation
X9522Dual Voltage MonitorsIntersil Corporation
Intersil Corporation

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar