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PDF X9455 Data sheet ( Hoja de datos )
| Número de pieza | X9455 | |
| Descripción | Dual Two-wiper Digitally-Controlled Potentiometer | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de X9455 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
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Dual Two-wiper Digitally-Controlled
(XDCP™) Potentiometer
The X9455 integrates 2 digitally controlled potentiometers
(XDCP), each one with dual wipers, on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented using
255 resistive elements in a series array. Between each
element are tap points connected to wiper terminals through
switches. The position of each wiper on the array is
controlled by the user through the U/D or 2-wire bus
interface. Each potentiometer wiper has associated with it
two volatile Wiper Counter Register (WCR) and each WCR
has associated with it four non-volatile Data Registers that
can be directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the resistor
array though the switches. The contents of the default data
registers (DR0A0, DR0B0, DR1A0, DR1B0) are loaded into
the WCR on power up.
The DCP can be used as a four-terminal potentiometer in a
wide variety of applications including the programming of
bias voltages, window comparators, and three resistor
programmable networks.
www.DataSheet4U.com
Pinout
X9455
(24 LD TSSOP)
TOP VIEW
DS0
A0
RW0B
NC
NC
U/D
Vcc
RL0
RH0
RW0A
A2
WP
1
2
3
4
5
6 X9455
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DS1
SCL
RL1
RH1
RW1A
CS
Vss
RW1B
NC
NC
A1
SDA
July 28, 2006
X9455
FN8202.1
Features
• Dual two-wiper solid state potentiometer
• 256 resistor tap points-0.4% resolution
• 2-wire serial interface for write, read, and transfer
operations of the potentiometer
• Up/Down interface for individual potentiometer wipers
• Wiper resistance, 40Ω typical
• Non-volatile storage of wiper positions
• Power on recall loads saved wiper position on power-up.
• Standby current < 20µA Max
• Maximum wiper current: 3mA
• VCC: 2.7V to 5.5V operation
• 2.8kΩ,10kΩ, 50kΩ, 100kΩ version of total pot resistance
• Endurance: 100,000 data changes per bit per register
• 100 yr. data retention
• 24 Ld TSSOP
• Pb-free plus anneal available (RoHS compliant)
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
X9455
DC Electrical Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN MAX
VIH Input HIGH voltage
VIL Input LOW voltage
VOL SDA pin output LOW voltage
IOL = 3mA
VCC x 0.7
-1
VCC + 1
VCC x 0.3
0.4
UNITS
V
V
V
Endurance and Data Retention
PARAMETER
Minimum endurance
Data retention
MIN
100,000
100
UNITS
Data changes per bit
Years
Capacitance
SYMBOL
TEST
CIN/OUT (Note 5) Input / Output capacitance (SDA)
CIN (Note 5) Input capacitance (DS0, DS1, CS, U/D, SCL, WP, A2, A1
and A0)
TEST CONDITIONS
VOUT = 0V
VIN = 0V
MAX
8
6
UNITS
pF
pF
Power-Up Timing
SYMBOL
PARAMETER
tD (Notes 5, 9) Power Up Delay from VCC power up (VCC above 2.7V) to wiper position recall
completed, and communication interfaces ready for operation.
MAX
2
UNITS
ms
A.C. Test Conditions
Input Pulse Levels
Input rise and fall times
Input and output timing threshold level
External load at pin SDA
2-Wire Interface Timing (s)
SYMBOL
PARAMETER
fSCL
Clock Frequency
tHIGH
Clock High Time
tLOW
Clock Low Time
tSU:STA Start Condition Setup Time
tHD:STA Start Condition Hold Time
tSU:STO Stop Condition Setup Time
tSU:DAT SDA Data Input Setup Time
tHD:DAT SDA Data Input Hold Time
tR (Note 5) SCL and SDA Rise Time
tF (Note 5) SCL and SDA Fall Time
tAA (Note 5) SCL Low to SDA Data Output Valid Time
tDH SDA Data Output Hold Time
tIN (Note 5) Pulse Width Suppression Time at SCL and SDA inputs
tBUF (Note 5) Bus Free Time (Prior to Any Transmission)
VCC x 0.1 to VCC x 0.9
10ns
VCC x 0.5
2.3kΩ to VCC and 100 pF to VSS
MIN
600
1300
600
600
600
100
30
0
1200
MAX
400
300
300
0.9
50
UNITS
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
5 FN8202.1
July 28, 2006
5 Page 
X9455
SCL
SDA
START
DATA
DATA
DATA
STABLE CHANGE STABLE
STOP
FIGURE 2. VALID DATA CHANGES, START, AND STOP CONDITIONS
2-Wire serial interface
Serial Stop Condition
Protocol Overview
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides the
clock for both transmit and receive operations. The X9455
operates as a slave in all applications.
All 2-wire interface operations must begin with a START,
followed by a Slave Address byte. The Slave Address
selects the X9455, and specifies if a Read or Write operation
is to be performed.
All communications must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH. The STOP condition is also used to place the
device into the Standby power mode after a read sequence.
A STOP condition can only be issued after the transmitting
device has released the bus (See Figure 2).
Serial Acknowledge
An ACK (Acknowledge), is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the bus after transmitting
eight bits. During the ninth clock cycle, the receiver pulls the
SDA line LOW to acknowledge the reception of the eight bits
of data (See Figure 3).
All Communication over the 2-wire interface is conducted by
sending the MSB of each byte of data first.
Serial Clock and Data
Data states on the SDA line can change only while SCL is
LOW. SDA state changes while SCL is HIGH are reserved
for indicating START and STOP conditions (See Figure 2).
On power up of the X9455, the SDA pin is in the input mode.
The device responds with an ACK after recognition of a
START condition followed by a valid Slave Address byte. A
valid Slave Address byte must contain the Device Type
Identifier 0101, and the Device Address bits matching the
logic state of pins A2, A1, and A0 (See Figure 4).
If a write operation is selected, the device responds with an
ACK after the receipt of each subsequent eight-bit word.
Serial Start Condition
All commands are preceded by the START condition, which
is a HIGH to LOW transition of SDA while SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command
until this condition has been met (See Figure 2).
In the read mode, the device transmits eight bits of data,
releases the SDA line, and then monitors the line for an
ACK. The device continues transmitting data if an ACK is
detected. The device terminates further data transmissions if
an ACK is not detected. The master must then issue a STOP
condition to place the device into a known state.
SCL from Master
SDA Output from
Transmitter
1
89
SDA Output from
Receiver
START
FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER
ACK
11 FN8202.1
July 28, 2006
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet X9455.PDF ] | |
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