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PDF X9261 Data sheet ( Hoja de datos )

Número de pieza X9261
Descripción Dual Digitally-Controlled Potentiometers
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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®
Data Sheet
X9261
Single Supply/Low Power/256-Tap/SPI Bus
October 12, 2006
FN8171.4
Dual Digitally-Controlled (XDCP™)
Potentiometers
FEATURES
• Dual–Two Separate Potentiometers
• 256 Resistor Taps/pot–0.4% Resolution
• SPI Serial Interface for Write, Read, and Transfer
Operations of the Potentiometer Single Supply
Device
• Wiper Resistance, 100Ω typical @ VCC = 5V
• 4 Nonvolatile Data Registers for Each
Potentiometer
• Nonvolatile Storage of Multiple Wiper Positions
• Power-on Recall Loads Saved Wiper Position on
Power-up.
• Standby Current < 5µA Max
• 50kΩ, 100kΩ Versions of End to End Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes per Bit per
Register
• 24 Ld SOIC, 24 Ld TSSOP
• Low Power CMOS
www.DataSheet4U.com
Power Supply VCC =
Pb-Free Plus Anneal
5V ±10%
Available
(RoHS
Compliant)
FUNCTIONAL DIAGRAM
DESCRIPTION
The X9261 integrates 2 digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integrated circuit.
The digital controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
SPI bus interface. Each potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and
four non-volatile Data Registers that can be directly
written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor
array though the switches. Powerup recalls the
contents of the default Data Register (DR0) to the
WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
VCC
RH0
RH1
SPI
Bus
Interface
Address
Data
Status
Bus
Interface
and Control
Write
Read
Transfer
Inc/Dec
Control
Power-on Recall
Wiper Counter
Register (WCR)
Data Registers
(DR0-DR3)
VSS
RW0 RL0 RW1 RL1
50kΩ or 100kΩ versions
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 page




X9261 pdf
X9261
Figure 1. Detailed Potentiometer Block Diagram
One of Two Potentiometers
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
REGISTER 0
(DR0)
8
REGISTER 2
(DR2)
IF WCR = 00[H] THEN RW = RL
IF WCR = FF[H] THEN RW = RH
REGISTER 1
(DR1)
8
REGISTER 3
(DR3)
SERIAL
BUS
INPUT
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
(WCR)
UP/DN
MODIFIED SCK
INC/DEC
LOGIC
UP/DN
CLK
C
O
U
N
T
E
R
D
E
C
O
D
E
RH
RL
DEVICE DESCRIPTION
Wiper Counter Register (WCR)
The X9261 contains two Wiper Counter Registers, one
for each DCP potentiometer. The Wiper Counter
Register can be envisioned as a 8-bit parallel and
serial load counter with its outputs decoded to select
one of 256 switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction (See Instruction section for more details).
Finally, it is loaded with the contents of its Data
Register zero (DR0) upon power-up.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9261 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Power-up guidelines are recommended to ensure
proper loadings of the DR0 value into the WCR.
RW
Data Registers (DR)
Each potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a nonvolatile operation and will take
a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Bits [7:0] are used to store one of the 256 wiper
positions or data (0~255).
Status Register (SR)
This 1-bit Status Register is used to store the system
status.
WIP: Write In Progress status bit, read only.
– When WIP=1, indicates that high-voltage write cycle
is in progress.
– When WIP=0, indicates that no high-voltage write
cycle is in progress.
5 FN8171.4
October 12, 2006

5 Page





X9261 arduino
X9261
Write Data Register (DR)
Device Type Device Instruction DR and WCR
Data Byte
Identifier Addresses Opcode
CS
Addresses
(Sent by Host on SI)
CS
Falling
Edge
0
1
0
1 0 0 A1 A0 1 1 0 0 RB RA
0
P0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Rising
Edge
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
CS
Falling
Edge
Device Type
Identifier
0101
Device
Addresses
0 0 A1 A0
Instruction
Opcode
0001
DR
Addresses
RB RA 0 0
CS
Rising
Edge
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
CS Device Type Device
Instruction
DR
CS
Falling Identifier
Addresses
Opcode
Addresses Rising
Edge 0 1 0 1 0 0 A1 A0 1 0 0 0 RB RA 0 0 Edge
HIGH-VOLTAGE
WRITE CYCLE
Transfer Wiper Counter Register (WCR) to Data Register (DR)
CS Device Type Device
Instruction DR and WCR CS
Falling Identifier Addresses Opcode
Addresses Rising
Edge 0 1 0 1 0 0 A1 A0 1 1 1 0 RB RA 0 P0 Edge
HIGH-VOLTAGE
WRITE CYCLE
Transfer Data Register (DR) to Wiper Counter Register (WCR)
CS Device Type
Device
Instruction DR and WCR CS
Falling Identifier
Addresses
Opcode
Addresses Rising
Edge 0 1 0 1 0 0 A1 A0 1 1 0 1 RB RA 0 P0 Edge
Increment/Decrement Wiper Counter Register (WCR)
CS Device Type
Device
Instruction
WCR
Increment/Decrement
CS
Falling Identifier
Addresses
Opcode
Addresses
(Sent by Master on SDA) Rising
Edge 0 1 0 1 0 0 A1 A0 0 0 1 0 X X 0 P0 I/D I/D . . . . I/D I/D Edge
Read Status Register (SR)
CS Device Type
Device
Instruction
WCR
Data Byte
Falling Identifier
Addresses
Opcode Addresses
(Sent by X9261 on SO)
Edge 0 1 0 1 0 0 A1 A0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 WIP
CS
Rising
Edge
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Counter Register
(2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
11 FN8171.4
October 12, 2006

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