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PDF LM2501 Data sheet ( Hoja de datos )
| Número de pieza | LM2501 | |
| Descripción | Mobile Pixel Link (MPL) Camera Interface Serializer and Deserializer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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ADVANCE INFORMATION
June 2004
LM2501
Mobile Pixel Link (MPL) Camera Interface Serializer and
Deserializer
General Description
The LM2501 device is a Serializer/Deserializer that adapts
existing video busses to Mobile Pixel Link (MPL). MPL is
intended to replace wide LVCMOS video interfaces inside
portable electronics equipment benefiting their cost, size,
EMI and power consumption.
By using the LM2501 SERDES chipset, the interconnect is
reduced from 12 active signals to only 3 active signals
providing a 75% reduction. This eases interconect and flex
design, size and cost.
Contained in a 24 lead Ultra Thin CSP Package, the Serial-
izer resides beside the video source (camera) and translates
the parallel bus from LVCMOS levels to serial MPL levels for
transmission over a flex cable to the Deserializer located by
the respective destination Video Input Port.
An extra clock transport is provided to deliver a clock signal
to the target. For example, from the main board to the flip
board where the camera module is located. Transmission of
the clock also benefits from MPL’s low power transmission
and low EMI.
The Power_Down (PD*) input controls the power state of the
MPL interface. When PD* is asserted, the MD, MC and WC
signals are powered down to save current and reduce power
dissipation.
Features
n 160 Mbps Raw Throughput
n MPL-0 Meets MPL Physical Layer Specification
n Configurable as a Serializer or Deserializer
n Complete LVCMOS to MPL Translation
n Serializes 8-bit Camera Interface
— 8-bit color data
— plus VSYNC and HSYNC bits
n Link power down mode reduces quiescent power under
∼ 10 µA (actual TBD)
n 1.7V–3.1V and 2.9-3.1V Supply Voltage
n Interfaces to 1.8V–3.0V Logic
n Offered in a small 24L UCSP Package
— 3.5 mm X 4.5 mm
— 0.6 mm Max Height
System Benefits
n Reduced Wire Interface
n Low Power
n Low EMI
n Extra Clock Transport
n Intrinsic Level Translation
Typical Application Diagram
Ordering Information
NSID
LM2501SL
Package Type
24-Lead Ultra Thin CSP 3.5 X 4.5 X 0.6 mm
I2C® is a registered trademark of Phillips Corporation.
© 2004 National Semiconductor Corporation DS200916
20091601
Package ID
SLE24A
www.national.com
1 page  
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2)
Symbol
Parameter
Conditions
Min Typ
PARALLEL BUS TIMING
tSET Set Time - Data to Clock
tHOLD
Hold Time - Clock to Data
tRISE
Rise Time
tFALL
Fall Time
PCLOW
PCLK Low
PCHIGH
PCLK High
tDVBC
Data Valid before Clock
tDVAC
Data Valid after Clock
SERIAL BUS TIMING
Inputs
Outputs,
CL = 15 pF
Figure 2
Figure 2
TBD
TBD
TBD
TBD
50
50
tDVBC
tDVAC
POWER UP TIMING (see Figures 5, 6)
Figure 1
t1
WC Start Up Delay
Figure 5
100
t2
WC Low Initialization Low Planned Rev G ES test Chip will
State
double WC cyc counts on T1 to T4
11 12
t3
WC Pulse Width High
(SER) parameters to support higher
11
12
t4 WC Low State
WC rates.
11 12
t5 WCIN to WCOUT Latency
(SER)
67
t6 TBD
t7
SER PLL Lock Time
Figure 6
t8 MC Low Initialization Low
State
9
4,096
11 12
t9 MC Pulse Width High
t10 MC Low State
t11 SER Latency
t12 DES Latency
POWER OFF TIMING
11 12
11 12
TBD
TBD
tPAZ Disable Time to Power Off
tPZA Enable Time from Power
Off
Max
Units
ns
ns
ns
ns
%
%
ns
ns
WCCYC
13 WCCYC
13 WCCYC
13 WCCYC
8 WCCYC
WCCYC
MCCYC
13 MCCYC
13 MCCYC
13 MCCYC
MCCYC
MCCYC
µs
µs
5 www.national.com
5 Page 
Functional Description (Continued)
CAMERA INTERFACE
The Camera Interface provides serialization of color and
control bits. The interface provides data transport in a single
direction. Byte alignment is provided by the intrinsic first
rising edge of the MC line. PCLK is required and must be
free-running. Data may be raw Bayer or BT656 color infor-
mation. Data is strobed on the rising-edge on the input to
the Serializer. Data is sent LSB first (D0).
MPL provides the data transport path, control of the Camera
device is provided by an I2C control bus.
FIGURE 8. Camera Mode Serial Interface
20091606
FIGURE 9. Parallel Bus Timing
20091607
11 www.national.com
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet LM2501.PDF ] | |
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