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PDF DS25BR150 Data sheet ( Hoja de datos )

Número de pieza DS25BR150
Descripción 3.125 Gbps LVDS Buffer
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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April 2007
DS25BR150
3.125 Gbps LVDS Buffer
General Description
The DS25BR150 is a single channel 3.125 Gbps LVDS buffer
optimized for high-speed signal transmission over printed cir-
cuit boards and balanced cables. Fully differential signal
paths ensure exceptional signal integrity and noise immunity.
The DS25BR150 is a buffer/repeater with very low power
consumption. Other LVDS devices with similar IO character-
istics and with signal conditioning features include the follow-
ing products. The DS25BR110 features four levels of
equalization for use as an optimized receiver device, the
DS25BR120 features four levels of pre-emphasis for use as
an optimized driver device, while the DS25BR100 features
both pre-emphasis and equalization for use as an optimized
repeater device.
Wide input common mode range allows the receiver to accept
signals with LVDS, CML and LVPECL levels; the output levels
are LVDS. A very small package footprint requires a minimal
space on the board while the flow-through pinout allows easy
board layout. The differential inputs and outputs are internally
terminated with a 100resistor to lower device input and out-
put return losses, reduce component count, and further min-
imize board space.
Features
DC - 3.125 Gbps low jitter, high noise immunity, low power
operation
On-chip 100 input and output termination minimizes
insertion and return losses, reduces component count and
minimizes board space
7 kV ESD on LVDS I/O pins protects adjoining
components
Small 3 mm x 3 mm LLP-8 space saving package
Applications
Clock or data buffering / repeating
OC-48 / STM-16 Clock or data buffering / repeating
Serial ATA (SATA-150 and SATA-300)
Fibre Channel (2GFC)
PCI Express
InfiniBand
FireWire
Typical Application
© 2007 National Semiconductor Corporation 300055
30005510
www.national.com

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DS25BR150 pdf
AC Electrical Characteristics (Note 11)
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 9, 10)
Symbol
Parameter
Conditions
Min Typ Max Units
LVDS OUTPUT AC SPECIFICATIONS (OUT+, OUT-)
tPHLD Differential Propagation Delay High to Low
tPLHD Differential Propagation Delay Low to High
tSKD1 Pulse Skew |tPLHD − tPHLD| (Note 12)
tSKD2 Part to Part Skew (Note 13)
tLHT Rise Time
tHLT Fall Time
JITTER PERFORMANCE (Figure 5)
RL = 100Ω
RL = 100Ω
370 520
355 520
15 100
45 160
80 150
80 150
ps
ps
ps
ps
ps
ps
tDJ1 Deterministic Jitter (Peak-to-Peak Value )
tDJ2 (Note 15)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
3.125 Gbps
11 33 ps
15 41 ps
tRJ1 Random Jitter (RMS Value)
tRJ2 (Note 14)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
1.25 GHz
1.5625 GHz
0.5 1
0.5 1
ps
ps
tTJ1 Total Jitter (Peak to Peak Value)
tTJ2 (Note 16)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
2.5 Gbps
3.125 Gbps
0.04
0.07
0.11
0.15
UIP-P
UIP-P
Note 9: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 10: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 11: Specification is guaranteed by characterization and is not tested in production.
Note 12: tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of
the same channel.
Note 13: tSKD2, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
Note 14: Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
Note 15: Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted
algebraically.
Note 16: Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted.
5 www.national.com

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DS25BR150 arduino
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number DS25BR150TSD
NS Package Number SDA08A
(See AN-1187 for PCB Design and Assembly Recommendations)
11 www.national.com

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