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PDF FIN12AC Data sheet ( Hoja de datos )
| Número de pieza | FIN12AC | |
| Descripción | uSerDes Low-Voltage 12-Bit Bi-Directional Serializer/Deserializer | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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December 2006
FIN12AC
µSerDes™ Low-Voltage 12-Bit Bi-Directional
Serializer/Deserializer with Multiple Frequency Ranges
tm
Features
■ Low power consumption
■ Fairchild proprietary low-power CTL interface
■ LVCMOS parallel I/O interface:
– 2mA source / sink current
– Over-voltage tolerant control signals
■ Parallel I/O power supply (VDDP) range between
1.65V and 3.6V
■ Analog power supply range of 2.5V to 3.05V
■ Multi-mode operation allows for a single device to
operate as Serializer or Deserializer
■ Internal PLL with no external components
■ Standby power-down mode support
■ Small footprint packaging:
– 32-terminal MLP and 42-ball BGA
■ Built-in differential termination
■ Supports external CKREF frequencies; 5MHz to 40MHz
■ Serialized data rate up to 560Mb/s
■ Voltage translation from 1.65V to 3.6V
Applications
■ Microcontroller or pixel interfaces
■ Image sensors
■ Small displays: LCD, cell phone, digital camera,
portable gaming, printer, PDA, video camera,
automotive
Description
The FIN12AC is a 12-bit serializer capable of running a
parallel frequency range between 5MHz and 40MHz.
The frequency range is selected by the S1 and S2 con-
trol signals. The bi-directional data flow is controlled
through use of a direction (DIRI) control pin. The devices
can be configured to operate in a unidirectional mode
only by hardwiring the DIRI pin. An internal Phase-
Locked Loop (PLL) generates the required bit clock fre-
quency for transfer across the serial link. Options exist
for dual or single PLL operation, dependent upon system
operational parameters. The device has been designed
for low power operation and utilizes Fairchild proprietary
low-power control Current Transistor Logic (CTL) inter-
face. The device also supports an ultra low power power-
down mode for conserving power in battery-operated
applications.
Ordering Information
Part Number
Package
FIN12ACGFX 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA),
JEDEC MO-195, 3.5mm Wide
FIN12ACMLX 32-Terminal Molded Leadless Package (MLP),
Quad, JEDEC MO-220, 5mm Square
Pb-Free
Yes
Yes
Operating
Temperature
Range
Packing
Method
-30°C to +70°C Tape and Reel
-30°C to +70°C Tape and Reel
µSerDesTM is a trademark of Fairchild Semiconductor Corporation.
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.0
www.fairchildsemi.com
1 page  
Serializer Operation Mode
The serializer configurations are described in the following sections. The basic serialization circuitry works similarly in
these modes, but the actual data and clock streams differ, dependent on whether CKREF is the same as the STROBE
signal. When it is stated that CKREF = STROBE, the CKREF and STROBE signals have an identical frequency of
operation, but may or may not be phase aligned. When it is stated that CKREF does not equal STROBE, each signal is
distinct and CKREF must be running at a frequency high enough to avoid any loss of data condition. CKREF must
never be a lower frequency than STROBE.
Serializer Operation: (Figure 3)
Modes 1, 2, 3
DIRI = 1,
CKREF = STROBE
The PLL must receive a stable CKREF signal to achieve lock prior to any valid
data being sent. During the PLL phase, STROBE should not be connected to the
CKREF signal.
Once the PLL is stable and locked, the device can begin to capture and serialize
data. Data is captured on the rising edge of the STROBE signal and serialized.
The serialized data stream is synchronized and sent source synchronously with a
bit clock with an embedded word boundary. When operating in this mode, the
internal deserializer circuitry is disabled, including the DS input buffer. The CKSI
serial inputs remain active to allow the pass through of the CKSI signal to the CKP
output. For more on this mode, please see the section on Passing a Word Clock.
If this mode is not needed, the CKSI inputs can either be driven to valid levels or
left to float. For lowest power operation, let the CKSI inputs float.
DP[1:12] WORD n-1
WORD n
WORD n+1
CKREF/STROBE
DSO b12 b13 b14 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b1 b2 b3
CKSO
WORD n-2
WORD n-1
WORD n
Figure 3. Serializer Timing Diagram (CKREF = STROBE)
Serializer Operation: (Figure 4)
DIRI = 1,
CKREF does not = STROBE
If the same signal is not used for CKREF and STROBE, the CKREF signal must
be run at a higher frequency than the STROBE rate to serialize the data correctly.
The actual serial transfer rate remains at 14 times the CKREF frequency. A data
value of zero is sent when no valid data is present in the serial bit stream. The
operation of the serializer otherwise remains the same.
The exact frequency that the reference clock needs is dependent upon the stabil-
ity of the CKREF and STROBE signal. If the source of the CKREF signal imple-
ments spread spectrum technology, the minimum frequency of this spread
spectrum clock should be used in calculating the ratio of STROBE frequency to
the CKREF frequency. Similarly if the STROBE signal has significant cycle-to-
cycle variation, the maximum cycle-to-cycle time needs to be factored into the
selection of the CKREF frequency.
CKREF
DP[1:12]
STROBE
WORD n–1
WORD n
WORD n+1
DSO
CKSO
b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14
b1 b2 b3
No Data
WORD n-1
No Data
WORD n
Figure 4. Serializer Timing Diagram (CKREF does not = STROBE)
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.0
5
www.fairchildsemi.com
5 Page 
STROBE Pass-Through Mode
For some applications, it is desirable to pass a word
clock across a differential signal pair in the opposite
direction of serialization. The FIN12AC supports this
mode of operation. Figure 5 in the application section
illustrates how to configure the devices for this mode.
The following describes how to enable this functionality.
For the deserializer:
1. DIRI = LOW
2. CKREF = LOW
3. Word clock should be connected to the STROBE.
This passes the STROBE signal out the CKSO port.
For the serializer:
1. Connect CKSO of the deserializer to CKSI of the
serializer.
2. CKSI passes the signal to CKP.
When PLL-bypass mode is used, the bit clock toggles on
the CKP signal.
Table 3. Control I/O
Mode Number
0
1, 2, 3
1, 2, 3
DIRI
x
0
1
DIRO
CKSO
CKP
Mode of Operation
ZZ
Z Power Down Mode: S2 = 0, S1 = 0
1 CKSO = STROBE Deserializer Deserializer: Any active mode
Output STROBE
0 Serializer
Output Bit Clock
CKSI
Serializer: Any active mode
Flex Circuit Design Guidelines
The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O flex cable.
The following best practices should be used when developing the flex cabling or Flex PCB:
■ Keep all four differential wires the same length.
■ Allow no noisy signals over or near differential serial wires. Example: No LVCMOS traces over differential wires.
■ Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom.
■ Do not place test points on differential serial wires.
■ Use differential serial wires a minimum of 2cm away from the antenna.
© 2006 Fairchild Semiconductor Corporation
FIN12AC Rev. 1.1.0
11
www.fairchildsemi.com
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet FIN12AC.PDF ] | |
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