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PDF X5001 Data sheet ( Hoja de datos )
| Número de pieza | X5001 | |
| Descripción | CPU Supervisor | |
| Fabricantes | Xicor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de X5001 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
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X5001
CPU Supervisor
Features
• 200ms Power On Reset Delay
• Low Vcc Detection and Reset Assertion
—Five Standard Reset Threshold Voltages
—Adjust Low Vcc Reset Threshold Voltage using
special programming sequence
—Reset Signal Valid to Vcc=1V
• Selectable Nonvolatile Watchdog Timer
—0.2, 0.6, 1.4 seconds
—Off selection
—Select settings through software
• Long Battery Life With Low Power Consumption
—<50µA Max Standby Current, Watchdog On
—<1µA Max Standby Current, Watchdog Off
• 2.7V to 5.5V Operation
• SPI Mode 0 interface
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down Protection Circuitry
—Watchdog Change Latch
• High Reliability
•www.DataSheet4U.com Available Packages
—8-Lead TSSOP
—8-Lead SOIC
—8 Pin PDIP
Block Diagram
DESCRIPTION
This device combines three popular functions, Power on
Reset, Watchdog Timer, and Supply Voltage Supervision
in one package. This combination lowers system cost,
reduces board space requirements, and increases reli-
ability.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. During a system failure,
the device will respond with a RESET signal after a
selectable time-out interval. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The user’s system is protected from low voltage condi-
tions by the device’s low Vcc detection circuitry. When
Vcc falls below the minimum Vcc trip point, the system is
reset. RESET is asserted until Vcc returns to proper
operating levels and stabilizes. Five industry standard
VTRIP thresholds are available, however, Xicor’s unique
circuits allow the thresold to be reprogrammed to meet
custom requirements or to fine-tune the threshold for
applications requiring higher precision.
The device utilizes Xicor’s proprietary Direct WriteTM cell
for the Watchdog TImer control bits and the VTRIP stor-
age element, providing a minimum endurance of
100,000 write cycles and a minimum data retention of
100 years.
SI
SO
SCK
CS/WDI
VCC
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
WATCHDOG
TRANSITION
DETECTOR
VTRIP
+
-
©Xicor, Inc. 1994, 1995, 1996, 1998 Patents Pending
7078 1.1 8/9/99 CM
1
WATCHDOG
TIMER
RESET &
WATCHDOG
TIMEBASE
POWER ON/
LOW VOLTAGE
RESET
GENERATION
RESET
Characteristics subject to change without notice
7036 FRM 01
1 page  
X5001
Figure 5. Vtrip Programming Sequence
New Vcc applied =
Old Vcc applied + Error
Vtrip Programming
Execute
Reset Vtrip
Sequence
Set Vcc = Vcc applied =
Desired Vtrip
Execute
Set Vtrip
Sequence
Apply 5V to Vcc
Decrement Vcc
(Vcc = Vcc - 50mV)
New Vcc applied =
Old Vcc applied - Error
Execute
Reset Vtrip
Sequence
NO
Error < 0
RESET pin
goes active?
YES
Measured Vtrip -
Desired Vtrip
Error > 0
Error = 0
DONE
5
5 Page 
X5001
Figure 1. Data Output Timing
CS
SCK
SO
t CYC
tV
MSB OUT
MSB–1 OUT
tHO
tWH
t WL
t LAG
LSB OUT
tDIS
SI
ADDR
LSB IN
Figure 2. Data Input Timing
CS
SCK
SI
tLEAD
tSU t H
MSB IN
SO HIGH IMPEDANCE
tCS
tLAG
tRI t FI
LSB IN
Figure 1. Symbol Table
WAVEFORM INPUTS
OUTPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet X5001.PDF ] | |
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