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PDF X4285 Data sheet ( Hoja de datos )

Número de pieza X4285
Descripción (X4283 / X4285) CPU Supervisor
Fabricantes Intersil Corporation 
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®
Data Sheet
May 23, 2006
X4283, X4285
128K, 16K x 8 Bit
FN8121.1
CPU Supervisor with 128K EEPROM
FEATURES
• Selectable watchdog timer
• Low VCC detection and reset assertion
—Four standard reset threshold voltages
—Adjust low VCC reset threshold voltage using
special programming sequence
—Reset signal valid to VCC = 1V
• Low power CMOS
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog OFF
—3mA active current
• 128Kbits of EEPROM
—64 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512
bytes of EEPROM array with programmable
Block Lockprotection
• 400kHz 2-wire interface
www.DataSheet4U.com 2.7V to 5.5V power supply operation
• Available packages
—8 Ld SOIC
—8 Ld TSSOP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
DESCRIPTION
The X4283, X4285 combines four popular functions,
Power-on Reset Control, Watchdog Timer, Supply
Voltage Supervision, and Block Lock protect serial
EEPROM memory in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting
the system when VCC falls below the set minimum VCC
trip point. RESET/RESET is asserted until VCC returns
to proper operating level and stabilizes. Four industry
standard Vtrip thresholds are available, however, Inter-
sil’s unique circuits allow the threshold to be repro-
grammed to meet custom requirements or to fine-tune
the threshold for applications requiring higher precision.
WP
SDA
SCL
S0
S1
Watchdog Transition
Detector
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset logic
Protect Logic
Status
Register
EEPROM Array
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
RESET (X4283)
RESET (X4285)
Power-on and
VCC
VTRIP
+
-
Low Voltage
Reset
Generation
Kb=Kilobyte
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 page




X4285 pdf
X4283, X4285
PRINCIPLES OF OPERATION
Power-on Reset
Application of power to the X4283, X4285 activates a
Power-on Reset Circuit that pulls the RESET/RESET
pin active. This signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-
up.
When VCC exceeds the device VTRIP threshold value
for 200ms (nominal) the circuit releases
RESET/RESET allowing the system to begin opera-
tion.
LOW VOLTAGE MONITORING
During operation, the X4283, X4285 monitors the VCC
level and asserts RESET/RESET if supply voltage falls
below a preset minimum VTRIP. The RESET/RESET
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
It also remains active until VCC returns and exceeds
VTRIP for 200ms.
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to
LOW periodically, while SCL is HIGH (this is a start bit)
prior to the expiration of the watchdog time out period to
prevent a RESET/RESET signal. The state of two non-
volatile control bits in the Status Register determine
the watchdog timer period. The microprocessor can
change these watchdog bits, or they may be “locked”
by tying the WP pin HIGH.
EEPROM INADVERTENT WRITE PROTECTION
When RESET/RESET goes active as a result of a low
voltage condition or Watchdog Timer Time-Out, any
in-progress communications are terminated. While
RESET/RESET is active, no new communications are
allowed and no nonvolatile write operation can start.
Non-volatile writes in-progress when RESET/RESET
goes active are allowed to finish.
Additional protection mechanisms are provided with
memory Block Lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
VCC THRESHOLD RESET PROCEDURE
The X4283, X4285 is shipped with a standard VCC
threshold (VTRIP) voltage. This value will not change
over normal operating and storage conditions. How-
ever, in applications where the standard VTRIP is not
exactly right, or if higher precision is needed in the
VTRIP value, the X4283, X4285 threshold may be
adjusted. The procedure is described below, and uses
the application of a nonvolatile control signal.
Figure 1. Set VTRIP Level Sequence (VCC = desired VTRIP values WEL bit set)
WP VP = 12-15V
01234567 01234567
0 1 23 4 56 7
0123456 7
SCL
SDA
A0h
00h 01h
00h
5 FN8121.1
May 23, 2006

5 Page





X4285 arduino
X4283, X4285
Serial Write Operations
BYTE WRITE
For a write operation, the device requires the Slave
Address Byte and a Word Address Byte. This gives the
master access to any one of the words in the array.
After receipt of the Word Address Byte, the device
responds with an acknowledge, and awaits the next
Figure 8. Byte Write Sequence
eight bits of data. After receiving the 8 bits of the Data
Byte, the device again responds with an acknowledge.
The master then terminates the transfer by generating a
stop condition, at which time the device begins the inter-
nal write cycle to the nonvolatile memory. During this
internal write cycle, the device inputs are disabled, so the
device will not respond to any requests from the master.
The SDA output is at high impedance. See Figure 8.
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t Slave
a Address
r
t
10 1 0
Word Address
Byte 1
Word Address
Byte 0
0
AAA
CCC
KKK
Data
S
t
o
p
A
C
K
A write to a protected block of memory will suppress
the acknowledge bit.
Page Write
The device is capable of a page write operation. It is
initiated in the same manner as the byte write opera-
tion; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit
an unlimited number of 8-bit bytes. After the receipt of
each byte, the device will respond with an acknowl-
edge, and the address is internally incremented by
one. The page address remains constant. When the
counter reaches the end of the page, it “rolls over” and
goes back to ‘0’ on the same page. This means that
the master can write 64 bytes to the page starting at
any location on that page. If the master begins writing
at location 60, and loads 12 bytes, then the first 4
bytes are written to locations 60 through 63, and the
last 8 bytes are written to locations 0 through 7. After-
wards, the address counter would point to location 8 of
the page that was just written. If the master supplies
more than 64 bytes of data, then new data over-writes
the previous data, one byte at a time.
Figure 9. Page Write Operation
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
r
t
Slave
Address
Word Address
Byte 1
Word Address
Byte 0
10 10
0
AA
A
CC C
KK
K
Data
(1)
(1 < n < 64)
Data
(n)
A
C
K
S
t
o
p
A
C
K
11 FN8121.1
May 23, 2006

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