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PDF X40030 Data sheet ( Hoja de datos )

Número de pieza X40030
Descripción (X40030 - X40035) Triple Voltage Monitor
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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No Preview Available ! X40030 Hoja de datos, Descripción, Manual

®
PRELIMINARY
Data Sheet
X40030, X40031, X40034, X40035
May 25, 2006
FN8114.1
Triple Voltage Monitor with Integrated
CPU Supervisor
FEATURES
• Triple voltage detection and reset assertion
—Standard reset threshold settings
see selection table on page 5.
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to VCC = 1V
—Monitor three seperate voltages
• Fault detection register
• Selectable power on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval
(25ms, 200ms, 1.4s or off)
• Debounced manual reset input
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available in 14 Ld SOIC, TSSOP packages
www.DataSheet4U.com Monitor voltages: 5V to 0.9V
• Independent core voltage monitor
• Pb-free plus anneal available (RoHS compliant)
APPLICATIONS
• Communication equipment
—Routers, hubs, switches
—Disk arrays, network storage
BLOCK DIAGRAM
• Industrial systems
—Process control
—Intelligent instrumentation
• Computer systems
— Computers
—Network servers
DESCRIPTION
The X40030, X40031, X40034, X40035 combine
power-on reset control, watchdog timer, supply voltage
supervision, second and third voltage supervision, and
manual reset, in one package. This combination lowers
system cost, reduces board space requirements, and
increases reliability.
Applying voltage to VCC activates the power on reset cir-
cuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscillator
to stabilize before the processor can execute code.
Low VCC detection circuitry protects the user’s system
from low voltage conditions, resetting the system when
VCC falls below the minimum VTRIP1 point.
RESET/RESET is active until VCC returns to proper
operating level and stabilizes. A second and third voltage
monitor circuit tracks the unregulated supply to provide a
power fail warning or monitors different power supply
voltage. Three common low voltage combinations are
available, however, Intersil’s unique circuits allows the
threshold for either voltage monitor to be reprogrammed
to meet specific system level requirements or to fine-tune
the threshold for applications requiring higher precision.
V3MON
V2MON
V3LMoognicitor
+
-
V2LMogoincitor
VTRIP3
+
-
VCC or
V2MON*
VTRIP2
V3FAIL
V2FAIL
SDA
WP
SCL
VCC
(V1MON)
Data
Register
Command
Decode Test
& Control
Logic
Fault Detection
Register
Status
Register
VCCLoMgoicnitor
+
VTRIP1
-
Watchdog
and
Reset Logic
Power on,
Manual Reset
Low Voltage
Reset
Generation
WDO
MR
RESET
X40030/34
RESET
X40031/35
LOWLINE
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 page




X40030 pdf
X40030, X40031, X40034, X40035
A manual reset input provides debounce circuitry for
minimum reset component count.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
Device
Expected System
Voltages
V(tVrip) 1
X40030, X40031
-A
-B
-C
5V; 3V or 3.3V; 1.8V
5V; 3V; 1.8V
3.3V; 2.5V; 1.8V
2.0-4.75*
4.55-4.65*
4.35-4.45*
2.95-3.05*
X40034, X40035
-A
-B
-C
5V; 3.3V; 1.5V
5V; 3V or 3.3V; 1.5V
5V; 3V or 3.3V; 1.2V
2.0-4.75*
4.55-4.65*
4.55-4.65*
4.55-4.65*
*Voltage monitor requires VCC to operate. Others are independent of VCC
PIN CONFIGURATION
X40030, X40034
14-Pin SOIC, TSSOP
V2FAIL
V2MON
LOWLINE
NC
MR
RESET
VSS
1
2
3
4
5
6
7
14 VCC
13 WDO
12 V3FAIL
11 V3MON
10 WP
9 SCL
8 SDA
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
V(tVrip) 2
1.70-4.75
2.85-2.95
2.55-2.65
2.15-2.25
0.90-3.50
1.25-1.35
1.25-1.35
0.95-1.05
V(tVrip) 3
1.70-4.75
1.65-1.75
1.65-1.75
1.65-1.75
1.70-4.75
3.05-3.15
2.85-2.95
2.85-2.95
POR
(system)
RESET = X40030
RESET = X40031
RESET = X40030
RESET = X40031
X40031, X40035
14-Pin SOIC, TSSOP
V2FAIL
V2MON
LOWLINE
NC
1
2
3
4
14 VCC
13 WDO
12 V3FAIL
11 V3MON
MR
RESET
VSS
5
6
7
10 WP
9 SCL
8 SDA
PIN DESCRIPTION
Pin Name
Function
1 V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and
goes HIGH when V2MON exceeds VTRIP2. There is no power up reset delay circuitry on this pin.
2 V2MON V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to VSS or VCC when
not used. The V2MON comparator is supplied by V2MON (X40030, X40031) or by the VCC input
(X40034, X40035).
3
LOWLINE
Early
when
Low
VCC
VCC Detect.
> VTRIP1.
This
CMOS
output
signal
goes
LOW
when
VCC
<
VTRIP1
and
goes
high
4 NC No connect.
5 MR Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will
remain HIGH/LOW until the pin is released and for the tPURST thereafter.
6 RESET/ RESET Output. (X40031, X40035) This open drain pin is an active LOW output which goes LOW
RESET
whenever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active
for the programmed time period (tPURST) on power up. It will also stay active until manual reset is
released and for tPURST thereafter.
RESET Output. (X40030, X40034) This pin is an active HIGH CMOS output which goes HIGH
whenever VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active
for the programmed time period (tPURST) on power up. It will also stay active until manual reset is
released and for tPURST thereafter.
5 FN8114.1
May 25, 2006

5 Page





X40030 arduino
X40030, X40031, X40034, X40035
WD1, WD0: Watchdog Timer Bits (Nonvolatile)
The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.
WD1
0
0
1
1
WD0
0
1
0
1
Watchdog Time Out Period
1.4 seconds
200 milliseconds
25 milliseconds
disabled (factory setting)
Writing to the Control Registers
Changing any of the nonvolatile bits of the control and
trickle registers requires the following steps:
– Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceded by a start and ended with a stop).
– Write a 06H to the Control Register to set the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation proceeded by a start
and ended with a stop).
– Write one byte value to the Control Register that has
all the control bits set to the desired state. The Con-
trol register can be represented as qxys 001r in
binary, where xy are the WD bits, s is the BP bit and
qr are the power up bits. This operation proceeded
by a start and ended with a stop bit. Since this is a
nonvolatile write cycle it will take up to 10ms (max.)
to complete. The RWEL bit is reset by this cycle and
the sequence must be repeated to change the non-
volatile bits again. If bit 2 is set to ‘1’ in this third step
(qxys 011r) then the RWEL bit is set, but the WD1,
WD0, PUP1, PUP0, and BP bits remain unchanged.
Writing a second byte to the control register is not
allowed. Doing so aborts the write operation and
returns a NACK.
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, or
power cycling the device or attempting a write to a
write protected block.
To illustrate, a sequence of writes to the device con-
sisting of [02H, 06H, 02H] will reset all of the nonvola-
tile bits in the Control Register to 0. A sequence of
[02H, 06H, 06H] will leave the nonvolatile bits
unchanged and the RWEL bit remains set.
Notes: 1. tPURST is set to 200ms as factory default.
2. Watch Dog Timer bits are shipped
disabled.
FAULT DETECTION REGISTER (FDR)
The Fault Detection Register provides the user the
status of what causes the system reset active. The
Manual Reset Fail, Watchdog Timer Fail and Three
Low Voltage Fail bits are volatile
7 6 5 4 3 210
LV1F LV2F LV3F WDF MRF 0 0 0
The FDR is accessed with a special preamble in the
slave byte (1011) and is located at address 0FFh. It
can only be modified by performing a byte write opera-
tion directly to the address of the register and only one
data byte is allowed for each register write operation.
There is no need to set the WEL or RWEL in the
control register to access this FDR.
11 FN8114.1
May 25, 2006

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