|
|
PDF X28HC64 Data sheet ( Hoja de datos )
| Número de pieza | X28HC64 | |
| Descripción | Byte Alterable EEPROM | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de X28HC64 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
|
No Preview Available !
®
Data Sheet
June 7, 2006
X28HC64
64K, 8K x 8 Bit
FN8109.1
5 Volt, Byte Alterable EEPROM
FEATURES
• 70ns access time
• Simple byte and page write
—Single 5V supply
—No external high voltages or VPP control circuits
— Self-timed
—No erase before write
—No complex programming algorithms
—No overerase problem
• Low power CMOS
—40mA active current max.
—200µA standby current max.
• Fast write cycle times
—64-byte page write operation
—Byte or page write cycle: 2ms typical
—Complete memory rewrite: 0.25 sec. typical
—Effective byte write cycle time: 32µs typical
• Software data protection
• End of write detection
—DATA polling
—Toggle bit
www.DataSheet4U.com
PIN CONFIGURATIONS
Plastic DIP
Flat Pack
CERDIP
SOIC
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 X28HC64 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
LCC
PLCC
4 3 2 1 32 31 30
A6 5
29 A8
A5 6
28 A9
A4 7
27 A11
A3 8
A2 9
X28HC64
(Top View)
A1 10
26 NC
25 OE
24 A10
A0 11
23 CE
NC 12
22 I/O7
I/O0 13
21 I/O6
14 15 16 17 18 19 20
• High reliability
—Endurance: 1 million cycles
—Data retention: 100 years
• JEDEC approved byte-wide pin out
• Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X28HC64 is an 8K x 8 EEPROM, fabricated with
Intersil’s proprietary, high performance, floating gate
CMOS technology. Like all Intersil programmable non-
volatile memories, the X28HC64 is a 5V only device. It
features the JEDEC approved pinout for byte-wide
memories, compatible with industry standard RAMs.
The X28HC64 supports a 64-byte page write operation,
effectively providing a 32µs/byte write cycle, and
enabling the entire memory to be typically written in 0.25
seconds. The X28HC64 also features DATA Polling and
Toggle Bit Polling, two methods providing early end of
write detection. In addition, the X28HC64 includes a
user-optional software data protection mode that further
enhances Intersil’s hardware write protect capability.
Intersil EEPROMs are designed and tested for appli-
cations requiring extended endurance. Inherent data
retention is greater than 100 years.
A2
A1
A0
I/O 0
I/O 1
I/O 2
NC
VSS
NC
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CE
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP
X28HC64
PGA
I/O1 I/O2 I/O3 I/O5 I/O6
12 13 15 17 18
I/O0 A0
11 10
VSS I/O4 I/O7
14 16 19
A1 A2
CE A10
98
20 21
X28HC64
A3
7
A4
6
(BOTT OM
OE
22
A11
23
VIEW)
A5 A12 VCC A9
A8
5 2 28 24 25
A6 A7
NC WE NC
4 3 1 27 26
Bottom View
32 A 3
31 A 4
30 A 5
29 A 6
28 A 7
27 A 12
26 NC
25 NC
24 VCC
23 NC
22 WE
21 NC
20 A 8
19 A 9
18 A11
17 OE
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
X28HC64
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE
LOW. The read operation is terminated by either CE or
OE returning HIGH. This two line control architecture
eliminates bus contention in a system environment.
The data bus will be in a high impedance state when
either OE or CE is HIGH.
Write
Write operations are initiated when both CE and WE
are LOW and OE is HIGH. The X28HC64 supports
both a CE and WE controlled write cycle. That is, the
address is latched by the falling edge of either CE or
WE, whichever occurs last. Similarly, the data is
latched internally by the rising edge of either CE or
WE, whichever occurs first. A byte write operation,
once initiated, will automatically continue to comple-
tion, typically within 2ms.
Page Write Operation
The page write feature of the X28HC64 allows the
entire memory to be written in 0.25 seconds. Page write
allows two to sixty-four bytes of data to be consecutively
written to the X28HC64 prior to the commencement of
the internal programming cycle. The host can fetch data
from another device within the system during a page
write operation (change the source address), but the
page address (A6 through A12) for each subsequent
valid write cycle to the part during this operation must
be the same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the
host can write an additional one to sixty-three bytes in
the same manner. Each successive byte load cycle,
started by the WE HIGH to LOW transition, must begin
within 100µs of the falling edge of the preceding WE. If
a subsequent WE HIGH to LOW transition is not
detected within 100µs, the internal automatic program-
ming cycle will commence. There is no page write win-
dow limitation. Effectively the page write window is
infinitely wide, so long as the host continues to access
the device within the byte load cycle time of 100µs.
Write Operation Status Bits
The X28HC64 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
I/O DP TB 5 4 3 2 1 0
Reserved
Toggle Bit
DATA Polling
DATA Polling (I/O7)
The X28HC64 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a sim-
ple bit test operation to determine the status of the
X28HC64, eliminating additional interrupt inputs or
external hardware. During the internal programming
cycle, any attempt to read the last byte written will pro-
duce the complement of that data on I/O7 (i.e. write
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O7 will reflect true data.
Toggle Bit (I/O6)
The X28HC64 also provides another method for deter-
mining when the internal write cycle is complete. Dur-
ing the internal programming cycle I/O6 will toggle
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
5 FN8109.1
June 7, 2006
5 Page 
X28HC64
SYSTEM CONSIDERATIONS
Because the X28HC64 is frequently used in large
memory arrays, it is provided with a two-line control
architecture for both read and write operations. Proper
usage can provide the lowest possible power dissipa-
tion, and eliminate the possibility of contention where
multiple I/O pins share the same bus.
To gain the most benefit, it is recommended that CE
be decoded from the address bus, and be used as the
primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation, this assures that all deselected
devices are in their standby mode, and that only the
selected device(s) is/are outputting data on the bus.
Because the X28HC64 has two power modes,
standby and active, proper decoupling of the memory
array is of prime concern. Enabling CE will cause tran-
sient current spikes. The magnitude of these spikes is
dependent on the output capacitive loading of the I/Os.
Therefore, the larger the array sharing a common bus,
the larger the transient spikes. The voltage peaks
associated with the current transients can be sup-
pressed by the proper selection and placement of
decoupling capacitors. As a minimum, it is recom-
mended that a 0.1µF high frequency ceramic capacitor
be used between VCC and VSS at each device.
Depending on the size of the array, the value of the
capacitor may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between VCC and VSS for
each eight devices employed in the array. This bulk
capacitor is employed to overcome the voltage droop
caused by the inductive effects of the PC board traces.
Normalized ICC(RD) by Temperature
Over Frequency
1.4
5.5 VCC
1.2 - 55°C
+ 25°C
1.0 + 125°C
0.8
0.6
0.4
0.2
0
10
Frequency (MHz)
20
Normalized ICC(RD) @ 25% Over
the VCC Range and Frequency
1.4
1.2
1.0
0.8
5.5 VCC
5.0 VCC
4.5 VCC
0.6
0.4
0.2
0
10
Frequency (MHz)
20
11 FN8109.1
June 7, 2006
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet X28HC64.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| X28HC64 | 5 Volt/ Byte Alterable E2PROM |  Xicor |
| X28HC64 | Byte Alterable EEPROM | Intersil Corporation |
| X28HC64D-12 | 5 Volt/ Byte Alterable E2PROM | Xicor |
| X28HC64D-50 | 5 Volt/ Byte Alterable E2PROM | Xicor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |